+
+// All entries are little endian.
+
+// if you increase that, you will also need to update the linker script file
+#ifdef SAMD21
+#define APP_START_ADDRESS 0x00002000
+#define UF2_FAMILY 0x68ed2b88
+#endif
+#ifdef SAMD51
+#define APP_START_ADDRESS 0x00004000
+#define UF2_FAMILY 0x55114460
+#endif
+
+#define UF2_MAGIC_START0 0x0A324655UL // "UF2\n"
+#define UF2_MAGIC_START1 0x9E5D5157UL // Randomly selected
+#define UF2_MAGIC_END 0x0AB16F30UL // Ditto
+
+// If set, the block is "comment" and should not be flashed to the device
+#define UF2_FLAG_NOFLASH 0x00000001
+#define UF2_FLAG_FAMILYID_PRESENT 0x00002000
+
+#define UF2_IS_MY_FAMILY(bl) \
+ (((bl)->flags & UF2_FLAG_FAMILYID_PRESENT) == 0 || (bl)->familyID == UF2_FAMILY)
+
+typedef struct {
+ // 32 byte header
+ uint32_t magicStart0;
+ uint32_t magicStart1;
+ uint32_t flags;
+ uint32_t targetAddr;
+ uint32_t payloadSize;
+ uint32_t blockNo;
+ uint32_t numBlocks;
+ uint32_t familyID;
+
+ // raw data;
+ uint8_t data[476];
+
+ // store magic also at the end to limit damage from partial block reads
+ uint32_t magicEnd;
+} UF2_Block;
+
+typedef struct {
+ uint8_t version;
+ uint8_t ep_in;
+ uint8_t ep_out;
+ uint8_t reserved0;
+ uint32_t cbw_tag;
+ uint32_t blocks_remaining;
+ uint8_t *buffer;
+} UF2_HandoverArgs;
+
+typedef void (*UF2_MSC_Handover_Handler)(UF2_HandoverArgs *handover);
+typedef void (*UF2_HID_Handover_Handler)(int ep);
+
+// this is required to be exactly 16 bytes long by the linker script
+typedef struct {
+ const uint32_t *config_data;
+ UF2_HID_Handover_Handler handoverHID;
+ UF2_MSC_Handover_Handler handoverMSC;
+ const char *info_uf2;
+} UF2_BInfo;
+
+#define UF2_BINFO ((UF2_BInfo *)(APP_START_ADDRESS - sizeof(UF2_BInfo)))
+
+static inline bool is_uf2_block(void *data) {
+ UF2_Block *bl = (UF2_Block *)data;
+ return bl->magicStart0 == UF2_MAGIC_START0 && bl->magicStart1 == UF2_MAGIC_START1 &&
+ bl->magicEnd == UF2_MAGIC_END;
+}
+
+static inline bool in_uf2_bootloader_space(const void *addr) {
+ return 0xb4 <= (uint32_t)addr && (uint32_t)addr < APP_START_ADDRESS;
+}
+
+static inline const char *uf2_info(void) {
+ if (in_uf2_bootloader_space(UF2_BINFO->info_uf2))
+ return UF2_BINFO->info_uf2;
+ return "N/A";
+}
+
+#ifdef UF2_DEFINE_HANDOVER
+static inline void hf2_handover(uint8_t ep) {
+ const char *board_info = UF2_BINFO->info_uf2;
+ UF2_HID_Handover_Handler fn = UF2_BINFO->handoverHID;
+
+ if (in_uf2_bootloader_space(board_info) && in_uf2_bootloader_space((const void *)fn) &&
+ ((uint32_t)fn & 1)) {
+ // Pass control to bootloader; never returns
+ fn(ep & 0xf);
+ }
+}
+
+// the ep_in/ep_out are without the 0x80 mask
+// cbw_tag is in the same bit format as it came
+static inline void check_uf2_handover(uint8_t *buffer, uint32_t blocks_remaining, uint8_t ep_in,
+ uint8_t ep_out, uint32_t cbw_tag) {
+ if (!is_uf2_block(buffer))
+ return;
+
+ const char *board_info = UF2_BINFO->info_uf2;
+ UF2_MSC_Handover_Handler fn = UF2_BINFO->handoverMSC;
+
+ if (in_uf2_bootloader_space(board_info) && in_uf2_bootloader_space((const void *)fn) &&
+ ((uint32_t)fn & 1)) {
+ UF2_HandoverArgs hand = {
+ 1, ep_in, ep_out, 0, cbw_tag, blocks_remaining, buffer,
+ };
+ // Pass control to bootloader; never returns
+ fn(&hand);
+ }
+}
+#endif
+
+#endif
diff --git a/bootloader/inc/uf2hid.h b/bootloader/inc/uf2hid.h
new file mode 100644
index 0000000..90077b7
--- /dev/null
+++ b/bootloader/inc/uf2hid.h
@@ -0,0 +1,107 @@
+#ifndef UF2_HID_H
+#define UF2_HID_H 1
+
+#define HF2_CMD_BININFO 0x0001
+// no arguments
+#define HF2_MODE_BOOTLOADER 0x01
+#define HF2_MODE_USERSPACE 0x02
+struct HF2_BININFO_Result {
+ uint32_t mode;
+ uint32_t flash_page_size;
+ uint32_t flash_num_pages;
+ uint32_t max_message_size;
+ uint32_t uf2_family;
+};
+
+#define HF2_CMD_INFO 0x0002
+// no arguments
+// results is utf8 character array
+
+#define HF2_CMD_RESET_INTO_APP 0x0003
+// no arguments, no result
+
+#define HF2_CMD_RESET_INTO_BOOTLOADER 0x0004
+// no arguments, no result
+
+#define HF2_CMD_START_FLASH 0x0005
+// no arguments, no result
+
+#define HF2_CMD_WRITE_FLASH_PAGE 0x0006
+struct HF2_WRITE_FLASH_PAGE_Command {
+ uint32_t target_addr;
+ uint32_t data[0];
+};
+// no result
+
+#define HF2_CMD_CHKSUM_PAGES 0x0007
+struct HF2_CHKSUM_PAGES_Command {
+ uint32_t target_addr;
+ uint32_t num_pages;
+};
+struct HF2_CHKSUM_PAGES_Result {
+ uint16_t chksums[0 /* num_pages */];
+};
+
+#define HF2_CMD_READ_WORDS 0x0008
+struct HF2_READ_WORDS_Command {
+ uint32_t target_addr;
+ uint32_t num_words;
+};
+struct HF2_READ_WORDS_Result {
+ uint32_t words[0 /* num_words */];
+};
+
+#define HF2_CMD_WRITE_WORDS 0x0009
+struct HF2_WRITE_WORDS_Command {
+ uint32_t target_addr;
+ uint32_t num_words;
+ uint32_t words[0 /* num_words */];
+};
+// no result
+
+#define HF2_CMD_DMESG 0x0010
+// no arguments
+// results is utf8 character array
+
+typedef struct {
+ uint32_t command_id;
+ uint16_t tag;
+ uint8_t reserved0;
+ uint8_t reserved1;
+
+ union {
+ struct HF2_WRITE_FLASH_PAGE_Command write_flash_page;
+ struct HF2_WRITE_WORDS_Command write_words;
+ struct HF2_READ_WORDS_Command read_words;
+ struct HF2_CHKSUM_PAGES_Command chksum_pages;
+ };
+} HF2_Command;
+
+typedef struct {
+ uint16_t tag;
+ union {
+ struct {
+ uint8_t status;
+ uint8_t status_info;
+ };
+ uint16_t status16;
+ };
+ union {
+ struct HF2_BININFO_Result bininfo;
+ uint8_t data8[0];
+ uint16_t data16[0];
+ uint32_t data32[0];
+ };
+} HF2_Response;
+
+#define HF2_FLAG_SERIAL_OUT 0x80
+#define HF2_FLAG_SERIAL_ERR 0xC0
+#define HF2_FLAG_CMDPKT_LAST 0x40
+#define HF2_FLAG_CMDPKT_BODY 0x00
+#define HF2_FLAG_MASK 0xC0
+#define HF2_SIZE_MASK 63
+
+#define HF2_STATUS_OK 0x00
+#define HF2_STATUS_INVALID_CMD 0x01
+
+#endif
diff --git a/bootloader/inc/usart_sam_ba.h b/bootloader/inc/usart_sam_ba.h
new file mode 100644
index 0000000..f0eca98
--- /dev/null
+++ b/bootloader/inc/usart_sam_ba.h
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------------
+ * SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _USART_SAM_BA_H_
+#define _USART_SAM_BA_H_
+
+#include "stdbool.h"
+#include "stdint.h"
+
+/* USART buffer size (must be a power of two) */
+#define USART_BUFFER_SIZE 128
+
+/* Define the default time-out value for USART. */
+#define USART_DEFAULT_TIMEOUT 1000
+
+/* Xmodem related defines */
+/* CRC16 polynomial */
+#define CRC16POLY 0x1021
+
+#define SHARP_CHARACTER '#'
+
+/* X/Ymodem protocol: */
+#define SOH 0x01
+//#define STX 0x02
+#define EOT 0x04
+#define ACK 0x06
+#define NAK 0x15
+#define CAN 0x18
+#define ESC 0x1b
+
+#define PKTLEN_128 128
+
+/**
+ * \brief Open the given USART
+ */
+void usart_open(void);
+
+/**
+ * \brief Stops the USART
+ */
+void usart_close(void);
+
+/**
+ * \brief Puts a byte on usart line
+ *
+ * \param value Value to put
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+int usart_putc(int value);
+
+/**
+ * \brief Waits and gets a value on usart line
+ *
+ * \return value read on usart line
+ */
+int usart_getc(void);
+
+/**
+ * \brief Returns true if the SAM-BA Uart received the sharp char
+ *
+ * \return Returns true if the SAM-BA Uart received the sharp char
+ */
+int usart_sharp_received(void);
+
+/**
+ * \brief This function checks if a character has been received on the usart
+ * line
+ *
+ * \return \c 1 if a byte is ready to be read.
+ */
+bool usart_is_rx_ready(void);
+
+/**
+ * \brief Gets a value on usart line
+ *
+ * \return value read on usart line
+ */
+int usart_readc(void);
+
+/**
+ * \brief Send buffer on usart line
+ *
+ * \param data pointer
+ * \param number of data to send
+ * \return number of data sent
+ */
+uint32_t usart_putdata(void const *data, uint32_t length); // Send given data (polling)
+
+/**
+ * \brief Gets data from usart line
+ *
+ * \param data pointer
+ * \param number of data to get
+ * \return value read on usart line
+ */
+uint32_t usart_getdata(void *data, uint32_t length); // Get data from comm. device
+
+/**
+ * \brief Send buffer on usart line using Xmodem protocol
+ *
+ * \param data pointer
+ * \param number of data to send
+ * \return number of data sent
+ */
+uint32_t
+usart_putdata_xmd(void const *data,
+ uint32_t length); // Send given data (polling) using xmodem (if necessary)
+
+/**
+ * \brief Gets data from usart line using Xmodem protocol
+ *
+ * \param data pointer
+ * \param number of data to get
+ * \return value read on usart line
+ */
+uint32_t
+usart_getdata_xmd(void *data,
+ uint32_t length); // Get data from comm. device using xmodem (if necessary)
+
+/**
+ * \brief Gets data from usart line using Xmodem protocol
+ *
+ * \param data pointer
+ * \param number of data to get
+ * \return value read on usart line
+ */
+uint16_t add_crc(uint8_t ch, unsigned short crc0);
+
+uint8_t getPacket(uint8_t *pData, uint8_t sno);
+
+#endif // _USART_SAM_BA_H_
diff --git a/bootloader/include/board_config.h b/bootloader/include/board_config.h
new file mode 100644
index 0000000..9ef09f0
--- /dev/null
+++ b/bootloader/include/board_config.h
@@ -0,0 +1,56 @@
+/*
+ * Board config for the VersaPad v2 UF2 bootloader.
+ * Adapted from Microsoft uf2-samdx1 boards/gemma_m0/board_config.h
+ * (closest upstream template: crystalless ATSAMD21, same USB_VID).
+ */
+#ifndef BOARD_CONFIG_H
+#define BOARD_CONFIG_H
+
+#define CRYSTALLESS 1
+
+#define VENDOR_NAME "Custom"
+#define PRODUCT_NAME "VersaPad v2"
+#define VOLUME_LABEL "VERSABOOT"
+#define INDEX_URL "https://git.jappel.io/jappel/VersaMCU"
+#define BOARD_ID "SAMD21G17D-VersaPad-v2"
+
+/* Same VID as the app firmware (platformio.ini), distinct PID so the
+ * bootloader enumerates as a different USB device than the app.
+ *
+ * NOT 0x0011: that's Adafruit's own Gemma M0 bootloader PID (this file's
+ * upstream template), and Windows machines with an Adafruit driver already
+ * installed silently bind it as a "Adafruit Circuit Playground" COM port
+ * instead of exposing the VERSABOOT mass-storage volume. Confirmed on real
+ * hardware 2026-08-05. 0x0043 is app PID (0x0042) + 1, not a known
+ * third-party assignment. */
+#define USB_VID 0x239A
+#define USB_PID 0x0043
+
+/* No plain GPIO status LED on this board, only a WS2812 chain on PB22.
+ * The bootloader's LED_PIN code just toggles a digital output, that would
+ * not drive WS2812 correctly, so leave it undefined for now. */
+//#define LED_PIN
+//#define LED_TX_PIN
+//#define LED_RX_PIN
+
+//#define BOARD_RGBLED_CLOCK_PIN
+//#define BOARD_RGBLED_DATA_PIN
+
+/* Hardware bootloader entry, no dedicated reset/boot button on this PCB.
+ * Reuses the bottom-right Cherry MX key (key_id 24 in the app firmware,
+ * see src/config/pins.h) as a boot-hold key: held while the board resets
+ * or powers up -> stay in the bootloader. Checked in check_start_application()
+ * before the app is even validated, so it works regardless of app firmware
+ * state.
+ *
+ * Pin numbers are PORT-flat (group*32 + pin), matching PINOP()/PINCFG() in
+ * uf2.h: PA15 = 15, PA08 = 8.
+ *
+ * Matrix wiring (src/config/pins.h, src/hal/matrix.cpp): key_id 24 = COL4 x
+ * ROW4. COL4 has an external 10k pull-up to 3V3 (idle HIGH); ROW4 is driven
+ * LOW during the check, matching the app's own scan polarity.
+ */
+#define BOOT_KEY_ROW_PIN 15 // PA15 -- ROW4, driven LOW during the check
+#define BOOT_KEY_COL_PIN 8 // PA08 -- COL4, read back; LOW = key pressed
+
+#endif
diff --git a/bootloader/include/uf2_version.h b/bootloader/include/uf2_version.h
new file mode 100644
index 0000000..12f8e47
--- /dev/null
+++ b/bootloader/include/uf2_version.h
@@ -0,0 +1 @@
+#define UF2_VERSION_BASE "versapad-1"
diff --git a/bootloader/lib/cmsis/CMSIS/Include/arm_common_tables.h b/bootloader/lib/cmsis/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000..76aadca
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 31. July 2014
+* $Revision: V1.4.4
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/arm_const_structs.h b/bootloader/lib/cmsis/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000..217f1d5
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 31. July 2014
+* $Revision: V1.4.4
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/bootloader/lib/cmsis/CMSIS/Include/arm_math.h b/bootloader/lib/cmsis/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000..49e23ee
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/arm_math.h
@@ -0,0 +1,7544 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 12. March 2014
+* $Revision: V1.4.4
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 4.60.
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM_math.uvproj
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+ #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__ /* Cosmic */
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+ 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+ ((q15_t) (x >> 16) * (q15_t) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+ ((q15_t) (x >> 16) * (q15_t) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+ ((q15_t) x * (q15_t) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+ ((q15_t) x * (q15_t) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+ ((q15_t) x * (q15_t) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+ ((q15_t) x * (q15_t) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+ ((q15_t) x * (q15_t) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SXTB16(
+ q31_t x)
+ {
+
+ return ((((x << 24) >> 24) & 0x0000FFFF) |
+ (((x << 8) >> 8) & 0xFFFF0000));
+ }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD(S->A0, in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta =
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ */
+
+
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in > 0)
+ {
+
+// #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+
+
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+ || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20u);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20u);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return (acc << 2u);
+
+ }
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return (acc >> 36);
+
+ }
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return (acc >> 40);
+
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+ #ifdef ARM_MATH_CM4
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+//Exit low optimization region - place directly after end of function definition
+ #ifdef ARM_MATH_CM4
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+//Enter low optimization region - place directly above function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+ #ifdef ARM_MATH_CM4
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+//Exit low optimization region - place directly after end of function definition
+ #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+ #ifdef ARM_MATH_CM4
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+//Exit low optimization region - place directly after end of function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+ #define LOW_OPTIMIZATION_EXIT
+
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__) // Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_cm0.h b/bootloader/lib/cmsis/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000..5186cb4
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_cm0.h
@@ -0,0 +1,711 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V4.00
+ * @date 22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_cm0plus.h b/bootloader/lib/cmsis/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000..17e4398
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,822 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V4.00
+ * @date 22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_cm3.h b/bootloader/lib/cmsis/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000..e1357c6
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1650 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V4.00
+ * @date 22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_cm4.h b/bootloader/lib/cmsis/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..bb6be13
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1802 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.00
+ * @date 22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+#include /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_cm7.h b/bootloader/lib/cmsis/CMSIS/Include/core_cm7.h
new file mode 100644
index 0000000..242540f
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2221 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V4.00
+ * @date 01. September 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+ @{
+ */
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x07) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+#include /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x07)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x07)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1];
+ __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93];
+ __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15];
+ __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1];
+ __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1];
+ __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6];
+ __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1];
+ __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## Cache functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos )
+
+
+/** \brief Enable I-Cache
+
+ The function turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache(void)
+{
+ #if (__ICACHE_PRESENT == 1)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0; // invalidate I-Cache
+ SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Disable I-Cache
+
+ The function turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache(void)
+{
+ #if (__ICACHE_PRESENT == 1)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache
+ SCB->ICIALLU = 0; // invalidate I-Cache
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+ The function invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache(void)
+{
+ #if (__ICACHE_PRESENT == 1)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Enable D-Cache
+
+ The function turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache(void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ ccsidr = SCB->CCSIDR;
+ sets = CCSIDR_SETS(ccsidr);
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
+ ways = CCSIDR_WAYS(ccsidr);
+ wshift = __CLZ(ways) & 0x1f;
+
+ __DSB();
+
+ do { // invalidate D-Cache
+ int32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+ __DSB();
+
+ SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Disable D-Cache
+
+ The function turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache(void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ ccsidr = SCB->CCSIDR;
+ sets = CCSIDR_SETS(ccsidr);
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
+ ways = CCSIDR_WAYS(ccsidr);
+ wshift = __CLZ(ways) & 0x1f;
+
+ __DSB();
+
+ SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache
+
+ do { // clean & invalidate D-Cache
+ int32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+ The function invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache(void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ ccsidr = SCB->CCSIDR;
+ sets = CCSIDR_SETS(ccsidr);
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
+ ways = CCSIDR_WAYS(ccsidr);
+ wshift = __CLZ(ways) & 0x1f;
+
+ __DSB();
+
+ do { // invalidate D-Cache
+ int32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Clean D-Cache
+
+ The function cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache(void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ ccsidr = SCB->CCSIDR;
+ sets = CCSIDR_SETS(ccsidr);
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
+ ways = CCSIDR_WAYS(ccsidr);
+ wshift = __CLZ(ways) & 0x1f;
+
+ __DSB();
+
+ do { // clean D-Cache
+ int32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCCSW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+ The function cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ ccsidr = SCB->CCSIDR;
+ sets = CCSIDR_SETS(ccsidr);
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
+ ways = CCSIDR_WAYS(ccsidr);
+ wshift = __CLZ(ways) & 0x1f;
+
+ __DSB();
+
+ do { // clean & invalidate D-Cache
+ int32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_cmFunc.h b/bootloader/lib/cmsis/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000..d5e32c5
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V4.00
+ * @date 28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_cmInstr.h b/bootloader/lib/cmsis/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000..d14110b
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.00
+ * @date 28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function executes a exclusive LDR instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function executes a exclusive LDR instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function executes a exclusive LDR instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function executes a exclusive STR instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function executes a exclusive STR instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function executes a exclusive STR instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+/** \brief Rotate Right with Extend (32 bit)
+
+ This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief LDRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/** \brief LDRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function executes a exclusive LDR instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function executes a exclusive LDR instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function executes a exclusive LDR instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function executes a exclusive STR instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function executes a exclusive STR instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function executes a exclusive STR instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief Rotate Right with Extend (32 bit)
+
+ This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief LDRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_cmSimd.h b/bootloader/lib/cmsis/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 0000000..ee58eee
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.00
+ * @date 22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_sc000.h b/bootloader/lib/cmsis/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000..5d0219c
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_sc000.h
@@ -0,0 +1,842 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V4.00
+ * @date 22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (000) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154];
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bootloader/lib/cmsis/CMSIS/Include/core_sc300.h b/bootloader/lib/cmsis/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000..b6f6e8b
--- /dev/null
+++ b/bootloader/lib/cmsis/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1630 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V4.00
+ * @date 22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bootloader/lib/samd21/samd21a/include/component-version.h b/bootloader/lib/samd21/samd21a/include/component-version.h
new file mode 100644
index 0000000..dcf909b
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/component-version.h
@@ -0,0 +1,65 @@
+/**
+ * \file
+ *
+ * \brief Component version header file
+ *
+ * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \license_stop
+ *
+ */
+
+#ifndef _COMPONENT_VERSION_H_INCLUDED
+#define _COMPONENT_VERSION_H_INCLUDED
+
+#define COMPONENT_VERSION_MAJOR 1
+#define COMPONENT_VERSION_MINOR 2
+
+//
+// The COMPONENT_VERSION define is composed of the major and the minor version number.
+//
+// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
+// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION
+// is at least 8 digits long.
+//
+#define COMPONENT_VERSION 00010002
+
+//
+// The build number does not refer to the component, but to the build number
+// of the device pack that provides the component.
+//
+#define BUILD_NUMBER 276
+
+//
+// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
+//
+#define COMPONENT_VERSION_STRING "1.2"
+
+//
+// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
+//
+// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
+//
+// "%Y-%m-%d %H:%M:%S"
+//
+//
+#define COMPONENT_DATE_STRING "2017-02-07 19:08:26"
+
+#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
+
diff --git a/bootloader/lib/samd21/samd21a/include/component/ac.h b/bootloader/lib/samd21/samd21a/include/component/ac.h
new file mode 100644
index 0000000..80ea1ab
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/component/ac.h
@@ -0,0 +1,544 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_COMPONENT_
+#define _SAMD21_AC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2205
+#define REV_AC 0x111
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE _U(0x00) /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST (_U(0x1) << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE (_U(0x1) << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
+#define AC_CTRLA_RUNSTDBY_Msk (_U(0x1) << AC_CTRLA_RUNSTDBY_Pos)
+#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
+#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
+#define AC_CTRLA_LPMUX (_U(0x1) << AC_CTRLA_LPMUX_Pos)
+#define AC_CTRLA_MASK _U(0x87) /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE _U(0x00) /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk (_U(0x3) << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
+#define AC_CTRLB_MASK _U(0x03) /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE _U(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk (_U(0x3) << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
+#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk (_U(0x1) << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
+#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
+#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
+#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
+#define AC_EVCTRL_COMPEI_Msk (_U(0x3) << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
+#define AC_EVCTRL_MASK _U(0x0313) /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk (_U(0x3) << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
+#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk (_U(0x1) << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
+#define AC_INTENCLR_MASK _U(0x13) /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE _U(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk (_U(0x3) << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
+#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk (_U(0x1) << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
+#define AC_INTENSET_MASK _U(0x13) /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN:1; /*!< bit: 4 Window x */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk (_U(0x3) << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
+#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk (_U(0x1) << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
+#define AC_INTFLAG_MASK _U(0x13) /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE _U(0x00) /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk (_U(0x3) << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
+#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk (_U(0x3) << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
+#define AC_STATUSA_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSA) Signal is above window */
+#define AC_STATUSA_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
+#define AC_STATUSA_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK _U(0x33) /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE _U(0x00) /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk (_U(0x3) << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
+#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
+#define AC_STATUSB_SYNCBUSY (_U(0x1) << AC_STATUSB_SYNCBUSY_Pos)
+#define AC_STATUSB_MASK _U(0x83) /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */
+#define AC_STATUSC_RESETVALUE _U(0x00) /**< \brief (AC_STATUSC reset_value) Status C */
+
+#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */
+#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos)
+#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */
+#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
+#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
+#define AC_STATUSC_STATE_Msk (_U(0x3) << AC_STATUSC_STATE_Pos)
+#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
+#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
+#define AC_STATUSC_WSTATE0_Msk (_U(0x3) << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
+#define AC_STATUSC_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSC) Signal is above window */
+#define AC_STATUSC_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSC) Signal is inside window */
+#define AC_STATUSC_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSC) Signal is below window */
+#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_MASK _U(0x33) /**< \brief (AC_STATUSC) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0 (_U(0x1) << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk (_U(0x3) << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
+#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define AC_WINCTRL_WINTSEL0_BELOW_Val _U(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK _U(0x07) /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Enable */
+ uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
+ uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t OUT:2; /*!< bit: 16..17 Output */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE _U(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE (_U(0x1) << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE (_U(0x1) << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk (_U(0x3) << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
+#define AC_COMPCTRL_SPEED_LOW_Val _U(0x0) /**< \brief (AC_COMPCTRL) Low speed */
+#define AC_COMPCTRL_SPEED_HIGH_Val _U(0x1) /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk (_U(0x3) << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
+#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define AC_COMPCTRL_INTSEL_RISING_Val _U(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define AC_COMPCTRL_INTSEL_FALLING_Val _U(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define AC_COMPCTRL_INTSEL_EOC_Val _U(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk (_U(0x7) << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
+#define AC_COMPCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXNEG_GND_Val _U(0x4) /**< \brief (AC_COMPCTRL) Ground */
+#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */
+#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define AC_COMPCTRL_MUXNEG_DAC_Val _U(0x7) /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk (_U(0x3) << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
+#define AC_COMPCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP (_U(0x1) << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk (_U(0x3) << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
+#define AC_COMPCTRL_OUT_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_ASYNC_Val _U(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_SYNC_Val _U(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYST (_U(0x1) << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk (_U(0x7) << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
+#define AC_COMPCTRL_FLEN_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) No filtering */
+#define AC_COMPCTRL_FLEN_MAJ3_Val _U(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define AC_COMPCTRL_FLEN_MAJ5_Val _U(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_MASK _U(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE _U(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk (_U(0x3F) << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
+#define AC_SCALER_MASK _U(0x3F) /**< \brief (AC_SCALER) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
+ __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
+ RoReg8 Reserved2[0x1];
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
+ RoReg8 Reserved3[0x3];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved4[0x8];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_AC_COMPONENT_ */
diff --git a/bootloader/lib/samd21/samd21a/include/component/adc.h b/bootloader/lib/samd21/samd21a/include/component/adc.h
new file mode 100644
index 0000000..fe41521
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/component/adc.h
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_COMPONENT_
+#define _SAMD21_ADC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2204
+#define REV_ADC 0x120
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE _U(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST (_U(0x1) << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE (_U(0x1) << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY (_U(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_MASK _U(0x07) /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk (_U(0xF) << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
+#define ADC_REFCTRL_REFSEL_INT1V_Val _U(0x0) /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
+#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U(0x1) /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
+#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
+#define ADC_REFCTRL_REFSEL_AREFA_Val _U(0x3) /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_AREFB_Val _U(0x4) /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP (_U(0x1) << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK _U(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk (_U(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
+#define ADC_AVGCTRL_SAMPLENUM_1_Val _U(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */
+#define ADC_AVGCTRL_SAMPLENUM_2_Val _U(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */
+#define ADC_AVGCTRL_SAMPLENUM_4_Val _U(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */
+#define ADC_AVGCTRL_SAMPLENUM_8_Val _U(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */
+#define ADC_AVGCTRL_SAMPLENUM_16_Val _U(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */
+#define ADC_AVGCTRL_SAMPLENUM_32_Val _U(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */
+#define ADC_AVGCTRL_SAMPLENUM_64_Val _U(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */
+#define ADC_AVGCTRL_SAMPLENUM_128_Val _U(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */
+#define ADC_AVGCTRL_SAMPLENUM_256_Val _U(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */
+#define ADC_AVGCTRL_SAMPLENUM_512_Val _U(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk (_U(0x7) << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
+#define ADC_AVGCTRL_MASK _U(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
+#define ADC_SAMPCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk (_U(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
+#define ADC_SAMPCTRL_MASK _U(0x3F) /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
+ uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
+ uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE _U(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */
+#define ADC_CTRLB_DIFFMODE (_U(0x1) << ADC_CTRLB_DIFFMODE_Pos)
+#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ (_U(0x1) << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN (_U(0x1) << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
+#define ADC_CTRLB_CORREN (_U(0x1) << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk (_U(0x3) << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
+#define ADC_CTRLB_RESSEL_12BIT_Val _U(0x0) /**< \brief (ADC_CTRLB) 12-bit result */
+#define ADC_CTRLB_RESSEL_16BIT_Val _U(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */
+#define ADC_CTRLB_RESSEL_10BIT_Val _U(0x2) /**< \brief (ADC_CTRLB) 10-bit result */
+#define ADC_CTRLB_RESSEL_8BIT_Val _U(0x3) /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
+#define ADC_CTRLB_PRESCALER_Msk (_U(0x7) << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
+#define ADC_CTRLB_PRESCALER_DIV4_Val _U(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define ADC_CTRLB_PRESCALER_DIV8_Val _U(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define ADC_CTRLB_PRESCALER_DIV16_Val _U(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define ADC_CTRLB_PRESCALER_DIV32_Val _U(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define ADC_CTRLB_PRESCALER_DIV64_Val _U(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define ADC_CTRLB_PRESCALER_DIV128_Val _U(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define ADC_CTRLB_PRESCALER_DIV256_Val _U(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define ADC_CTRLB_PRESCALER_DIV512_Val _U(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
+#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_MASK _U(0x073F) /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
+#define ADC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
+
+#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
+#define ADC_WINCTRL_WINMODE_Msk (_U(0x7) << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
+#define ADC_WINCTRL_WINMODE_DISABLE_Val _U(0x0) /**< \brief (ADC_WINCTRL) No window mode (default) */
+#define ADC_WINCTRL_WINMODE_MODE1_Val _U(0x1) /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
+#define ADC_WINCTRL_WINMODE_MODE2_Val _U(0x2) /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
+#define ADC_WINCTRL_WINMODE_MODE3_Val _U(0x3) /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
+#define ADC_WINCTRL_WINMODE_MODE4_Val _U(0x4) /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
+#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_MASK _U(0x07) /**< \brief (ADC_WINCTRL) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE _U(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH (_U(0x1) << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */
+#define ADC_SWTRIG_START (_U(0x1) << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK _U(0x03) /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
+ uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
+ uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE _U(0x00000000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
+#define ADC_INPUTCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN8_Val _U(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN9_Val _U(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN10_Val _U(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN11_Val _U(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN12_Val _U(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN13_Val _U(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN14_Val _U(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN15_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN16_Val _U(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN17_Val _U(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN18_Val _U(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN19_Val _U(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Reference */
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
+#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U(0x1C) /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
+#define ADC_INPUTCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXNEG_GND_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define ADC_INPUTCTRL_MUXNEG_IOGND_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) I/O Ground */
+#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
+#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos)
+#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
+#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
+#define ADC_INPUTCTRL_GAIN_Msk (_U(0xF) << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
+#define ADC_INPUTCTRL_GAIN_1X_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) 1x */
+#define ADC_INPUTCTRL_GAIN_2X_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) 2x */
+#define ADC_INPUTCTRL_GAIN_4X_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) 4x */
+#define ADC_INPUTCTRL_GAIN_8X_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) 8x */
+#define ADC_INPUTCTRL_GAIN_16X_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) 16x */
+#define ADC_INPUTCTRL_GAIN_DIV2_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) 1/2x */
+#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_MASK _U(0x0FFF1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
+ uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */
+#define ADC_EVCTRL_STARTEI (_U(0x1) << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */
+#define ADC_EVCTRL_SYNCEI (_U(0x1) << ADC_EVCTRL_SYNCEI_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO (_U(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO (_U(0x1) << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK _U(0x33) /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
+#define ADC_INTENCLR_RESRDY (_U(0x1) << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
+#define ADC_INTENCLR_OVERRUN (_U(0x1) << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
+#define ADC_INTENCLR_WINMON (_U(0x1) << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define ADC_INTENCLR_SYNCRDY (_U(0x1) << ADC_INTENCLR_SYNCRDY_Pos)
+#define ADC_INTENCLR_MASK _U(0x0F) /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE _U(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY (_U(0x1) << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN (_U(0x1) << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON (_U(0x1) << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
+#define ADC_INTENSET_SYNCRDY (_U(0x1) << ADC_INTENSET_SYNCRDY_Pos)
+#define ADC_INTENSET_MASK _U(0x0F) /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
+ __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
+ __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
+ __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ __I uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */
+#define ADC_INTFLAG_RESRDY (_U(0x1) << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */
+#define ADC_INTFLAG_OVERRUN (_U(0x1) << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */
+#define ADC_INTFLAG_WINMON (_U(0x1) << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */
+#define ADC_INTFLAG_SYNCRDY (_U(0x1) << ADC_INTFLAG_SYNCRDY_Pos)
+#define ADC_INTFLAG_MASK _U(0x0F) /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE _U(0x00) /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */
+#define ADC_STATUS_SYNCBUSY (_U(0x1) << ADC_STATUS_SYNCBUSY_Pos)
+#define ADC_STATUS_MASK _U(0x80) /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */
+#define ADC_RESULT_RESETVALUE _U(0x0000) /**< \brief (ADC_RESULT reset_value) Result */
+
+#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk (_U(0xFFFF) << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
+#define ADC_RESULT_MASK _U(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk (_U(0xFFFF) << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
+#define ADC_WINLT_MASK _U(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk (_U(0xFFFF) << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
+#define ADC_WINUT_MASK _U(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk (_U(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
+#define ADC_GAINCORR_MASK _U(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
+#define ADC_OFFSETCORR_MASK _U(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
+ uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE _U(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
+#define ADC_CALIB_LINEARITY_CAL_Msk (_U(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos)
+#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
+#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
+#define ADC_CALIB_BIAS_CAL_Msk (_U(0x7) << ADC_CALIB_BIAS_CAL_Pos)
+#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
+#define ADC_CALIB_MASK _U(0x07FF) /**< \brief (ADC_CALIB) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN (_U(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK _U(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
+ RoReg8 Reserved1[0x2];
+ __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
+ RoReg8 Reserved2[0x3];
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
+ RoReg8 Reserved3[0x3];
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
+ RoReg8 Reserved4[0x1];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+ RoReg8 Reserved5[0x2];
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+ RoReg8 Reserved6[0x2];
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_ADC_COMPONENT_ */
diff --git a/bootloader/lib/samd21/samd21a/include/component/dac.h b/bootloader/lib/samd21/samd21a/include/component/dac.h
new file mode 100644
index 0000000..ba84975
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/component/dac.h
@@ -0,0 +1,271 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_COMPONENT_
+#define _SAMD21_DAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DAC Digital Analog Converter */
+/*@{*/
+
+#define DAC_U2214
+#define REV_DAC 0x110
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST (_U(0x1) << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
+#define DAC_CTRLA_ENABLE (_U(0x1) << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
+#define DAC_CTRLA_RUNSTDBY (_U(0x1) << DAC_CTRLA_RUNSTDBY_Pos)
+#define DAC_CTRLA_MASK _U(0x07) /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
+ uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
+ uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
+ uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
+ uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
+#define DAC_CTRLB_EOEN (_U(0x1) << DAC_CTRLB_EOEN_Pos)
+#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
+#define DAC_CTRLB_IOEN (_U(0x1) << DAC_CTRLB_IOEN_Pos)
+#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
+#define DAC_CTRLB_LEFTADJ (_U(0x1) << DAC_CTRLB_LEFTADJ_Pos)
+#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
+#define DAC_CTRLB_VPD (_U(0x1) << DAC_CTRLB_VPD_Pos)
+#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
+#define DAC_CTRLB_BDWP (_U(0x1) << DAC_CTRLB_BDWP_Pos)
+#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
+#define DAC_CTRLB_REFSEL_Msk (_U(0x3) << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
+#define DAC_CTRLB_REFSEL_INT1V_Val _U(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */
+#define DAC_CTRLB_REFSEL_AVCC_Val _U(0x1) /**< \brief (DAC_CTRLB) AVCC */
+#define DAC_CTRLB_REFSEL_VREFP_Val _U(0x2) /**< \brief (DAC_CTRLB) External reference */
+#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK _U(0xDF) /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
+ uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
+#define DAC_EVCTRL_STARTEI (_U(0x1) << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
+#define DAC_EVCTRL_EMPTYEO (_U(0x1) << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_MASK _U(0x03) /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN (_U(0x1) << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY (_U(0x1) << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define DAC_INTENCLR_SYNCRDY (_U(0x1) << DAC_INTENCLR_SYNCRDY_Pos)
+#define DAC_INTENCLR_MASK _U(0x07) /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE _U(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN (_U(0x1) << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY (_U(0x1) << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
+#define DAC_INTENSET_SYNCRDY (_U(0x1) << DAC_INTENSET_SYNCRDY_Pos)
+#define DAC_INTENSET_MASK _U(0x07) /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
+ __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
+ __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
+#define DAC_INTFLAG_UNDERRUN (_U(0x1) << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
+#define DAC_INTFLAG_EMPTY (_U(0x1) << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
+#define DAC_INTFLAG_SYNCRDY (_U(0x1) << DAC_INTFLAG_SYNCRDY_Pos)
+#define DAC_INTFLAG_MASK _U(0x07) /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE _U(0x00) /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
+#define DAC_STATUS_SYNCBUSY (_U(0x1) << DAC_STATUS_SYNCBUSY_Pos)
+#define DAC_STATUS_MASK _U(0x80) /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
+#define DAC_DATA_RESETVALUE _U(0x0000) /**< \brief (DAC_DATA reset_value) Data */
+
+#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
+#define DAC_DATA_DATA_Msk (_U(0xFFFF) << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
+#define DAC_DATA_MASK _U(0xFFFF) /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
+#define DAC_DATABUF_RESETVALUE _U(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk (_U(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
+#define DAC_DATABUF_MASK _U(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
+ __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
+ __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x1];
+ __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
+ RoReg8 Reserved2[0x2];
+ __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DAC_COMPONENT_ */
diff --git a/bootloader/lib/samd21/samd21a/include/component/dmac.h b/bootloader/lib/samd21/samd21a/include/component/dmac.h
new file mode 100644
index 0000000..1d7c8c0
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/component/dmac.h
@@ -0,0 +1,1072 @@
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_COMPONENT_
+#define _SAMD21_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2223
+#define REV_DMAC 0x100
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
+ uint16_t :5; /*!< bit: 3.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST (_U(0x1) << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE (_U(0x1) << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */
+#define DMAC_CTRL_CRCENABLE (_U(0x1) << DMAC_CTRL_CRCENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk (_U(0xF) << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
+#define DMAC_CTRL_MASK _U(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk (_U(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
+#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk (_U(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
+#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) No action */
+#define DMAC_CRCCTRL_CRCSRC_IO_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_MASK _U(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
+#define DMAC_CRCDATAIN_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
+#define DMAC_CRCCHKSUM_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY (_U(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO (_U(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_MASK _U(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN (_U(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK _U(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
+ uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */
+#define DMAC_QOSCTRL_RESETVALUE _U(0x15) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
+
+#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
+#define DMAC_QOSCTRL_WRBQOS_Msk (_U(0x3) << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
+#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
+#define DMAC_QOSCTRL_FQOS_Msk (_U(0x3) << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
+#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define DMAC_QOSCTRL_FQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define DMAC_QOSCTRL_FQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
+#define DMAC_QOSCTRL_DQOS_Msk (_U(0x3) << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
+#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define DMAC_QOSCTRL_DQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define DMAC_QOSCTRL_DQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_MASK _U(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE _U(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
+#define DMAC_SWTRIGCTRL_MASK _U(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
+ uint32_t :3; /*!< bit: 4.. 6 Reserved */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
+ uint32_t :3; /*!< bit: 20..22 Reserved */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
+ uint32_t :3; /*!< bit: 28..30 Reserved */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
+#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
+#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
+#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
+#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK _U(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :2; /*!< bit: 11..12 Reserved */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE _U(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk (_U(0xF) << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
+#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR (_U(0x1) << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL (_U(0x1) << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP (_U(0x1) << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR (_U(0x1) << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY (_U(0x1) << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND (_U(0x1) << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK _U(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE _U(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk (_U(0xFFF) << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
+#define DMAC_INTSTATUS_MASK _U(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk (_U(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
+#define DMAC_BUSYCH_MASK _U(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk (_U(0xFFF) << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
+#define DMAC_PENDCH_MASK _U(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE _U(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk (_U(0xF) << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
+#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk (_U(0x1F) << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
+#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY (_U(0x1) << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk (_U(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
+#define DMAC_ACTIVE_MASK _U(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk (_U(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
+#define DMAC_BASEADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk (_U(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
+#define DMAC_WRBADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */
+#define DMAC_CHID_RESETVALUE _U(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */
+
+#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
+#define DMAC_CHID_ID_Msk (_U(0xF) << DMAC_CHID_ID_Pos)
+#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
+#define DMAC_CHID_MASK _U(0x0F) /**< \brief (DMAC_CHID) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
+#define DMAC_CHCTRLA_RESETVALUE _U(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST (_U(0x1) << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE (_U(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_MASK _U(0x03) /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
+ uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
+ uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
+ uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
+ uint32_t :8; /*!< bit: 14..21 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
+ uint32_t CMD:2; /*!< bit: 24..25 Software Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
+#define DMAC_CHCTRLB_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
+
+#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
+#define DMAC_CHCTRLB_EVACT_Msk (_U(0x7) << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
+#define DMAC_CHCTRLB_EVACT_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_EVACT_TRIG_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
+#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
+#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
+#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_EVACT_RESUME_Val _U(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
+#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
+#define DMAC_CHCTRLB_EVIE (_U(0x1) << DMAC_CHCTRLB_EVIE_Pos)
+#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
+#define DMAC_CHCTRLB_EVOE (_U(0x1) << DMAC_CHCTRLB_EVOE_Pos)
+#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
+#define DMAC_CHCTRLB_LVL_Msk (_U(0x3) << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
+#define DMAC_CHCTRLB_LVL_LVL0_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
+#define DMAC_CHCTRLB_LVL_LVL1_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
+#define DMAC_CHCTRLB_LVL_LVL2_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
+#define DMAC_CHCTRLB_LVL_LVL3_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
+#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */
+#define DMAC_CHCTRLB_TRIGSRC_Msk (_U(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
+#define DMAC_CHCTRLB_TRIGACT_Msk (_U(0x3) << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
+#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
+#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
+#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk (_U(0x3) << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
+#define DMAC_CHCTRLB_CMD_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_CMD_RESUME_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK _U(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR (_U(0x1) << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL (_U(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP (_U(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK _U(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR (_U(0x1) << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL (_U(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP (_U(0x1) << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK _U(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
+ __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
+ __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
+#define DMAC_CHINTFLAG_TERR (_U(0x1) << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL (_U(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP (_U(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK _U(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */
+#define DMAC_CHSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
+
+#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND (_U(0x1) << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY (_U(0x1) << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
+#define DMAC_CHSTATUS_FERR (_U(0x1) << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_MASK _U(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID (_U(0x1) << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk (_U(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
+#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
+#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
+#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk (_U(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
+#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
+#define DMAC_BTCTRL_BLOCKACT_INT_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk (_U(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
+#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC (_U(0x1) << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC (_U(0x1) << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL (_U(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_DST_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define DMAC_BTCTRL_STEPSEL_SRC_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk (_U(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
+#define DMAC_BTCTRL_STEPSIZE_X1_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pvReserved13;
+ void* pvReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pvReserved21;
+ void* pvReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00008000) /* 32 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 512
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x1001030D)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21e16a.h b/bootloader/lib/samd21/samd21a/include/samd21e16a.h
new file mode 100644
index 0000000..7bb07c6
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21e16a.h
@@ -0,0 +1,552 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16A_
+#define _SAMD21E16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions
+ * This file defines all structures and symbols for SAMD21E16A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pvReserved13;
+ void* pvReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pvReserved21;
+ void* pvReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00010000) /* 64 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x1001030C)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21e17a.h b/bootloader/lib/samd21/samd21a/include/samd21e17a.h
new file mode 100644
index 0000000..df03735
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21e17a.h
@@ -0,0 +1,552 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17A_
+#define _SAMD21E17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions
+ * This file defines all structures and symbols for SAMD21E17A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pvReserved13;
+ void* pvReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pvReserved21;
+ void* pvReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x1001030B)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E17A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21e18a.h b/bootloader/lib/samd21/samd21a/include/samd21e18a.h
new file mode 100644
index 0000000..8e7bcb7
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21e18a.h
@@ -0,0 +1,552 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E18A_
+#define _SAMD21E18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions
+ * This file defines all structures and symbols for SAMD21E18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pvReserved13;
+ void* pvReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pvReserved21;
+ void* pvReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00040000) /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x1001030A)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E18A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21g15a.h b/bootloader/lib/samd21/samd21a/include/samd21g15a.h
new file mode 100644
index 0000000..5131ac4
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21g15a.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15A_
+#define _SAMD21G15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions
+ * This file defines all structures and symbols for SAMD21G15A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pvReserved21;
+ void* pvReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00008000) /* 32 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 512
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x10010308)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21g16a.h b/bootloader/lib/samd21/samd21a/include/samd21g16a.h
new file mode 100644
index 0000000..1021280
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21g16a.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16A_
+#define _SAMD21G16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions
+ * This file defines all structures and symbols for SAMD21G16A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pvReserved21;
+ void* pvReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00010000) /* 64 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x10010307)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21g17a.h b/bootloader/lib/samd21/samd21a/include/samd21g17a.h
new file mode 100644
index 0000000..dc3b161
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21g17a.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17A_
+#define _SAMD21G17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions
+ * This file defines all structures and symbols for SAMD21G17A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pvReserved21;
+ void* pvReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x10010306)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21g17au.h b/bootloader/lib/samd21/samd21a/include/samd21g17au.h
new file mode 100644
index 0000000..46225b3
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21g17au.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17AU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17AU_
+#define _SAMD21G17AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions
+ * This file defines all structures and symbols for SAMD21G17AU:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G17AU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x10010310)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17AU_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21g18a.h b/bootloader/lib/samd21/samd21a/include/samd21g18a.h
new file mode 100644
index 0000000..2840b6e
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21g18a.h
@@ -0,0 +1,564 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18A_
+#define _SAMD21G18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions
+ * This file defines all structures and symbols for SAMD21G18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pvReserved21;
+ void* pvReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00040000) /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x10010305)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21g18au.h b/bootloader/lib/samd21/samd21a/include/samd21g18au.h
new file mode 100644
index 0000000..82c2532
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21g18au.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18AU
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18AU_
+#define _SAMD21G18AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions
+ * This file defines all structures and symbols for SAMD21G18AU:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G18AU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00040000) /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x1001030F)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18AU_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21j15a.h b/bootloader/lib/samd21/samd21a/include/samd21j15a.h
new file mode 100644
index 0000000..80aba23
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21j15a.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J15A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15A_
+#define _SAMD21J15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions
+ * This file defines all structures and symbols for SAMD21J15A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00008000) /* 32 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 512
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x10010303)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J15A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21j16a.h b/bootloader/lib/samd21/samd21a/include/samd21j16a.h
new file mode 100644
index 0000000..b054d7e
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21j16a.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J16A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16A_
+#define _SAMD21J16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions
+ * This file defines all structures and symbols for SAMD21J16A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00010000) /* 64 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x10010302)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J16A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21j17a.h b/bootloader/lib/samd21/samd21a/include/samd21j17a.h
new file mode 100644
index 0000000..bc85d93
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21j17a.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J17A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17A_
+#define _SAMD21J17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions
+ * This file defines all structures and symbols for SAMD21J17A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00020000) /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x10010301)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J17A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/samd21j18a.h b/bootloader/lib/samd21/samd21a/include/samd21j18a.h
new file mode 100644
index 0000000..ee9a8fa
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/samd21j18a.h
@@ -0,0 +1,576 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J18A
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J18A_
+#define _SAMD21J18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions
+ * This file defines all structures and symbols for SAMD21J18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#if !defined(_UL)
+#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */
+#define _L(x) x ## L /**< C code: Long integer literal constant value */
+#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
+#endif
+#else
+#if !defined(_UL)
+#define _U(x) x /**< Assembler: Unsigned integer literal constant value */
+#define _L(x) x /**< Assembler: Long integer literal constant value */
+#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */
+#endif
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pvReservedM12;
+ void* pvReservedM11;
+ void* pvReservedM10;
+ void* pvReservedM9;
+ void* pvReservedM8;
+ void* pvReservedM7;
+ void* pvReservedM6;
+ void* pfnSVC_Handler;
+ void* pvReservedM4;
+ void* pvReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pvReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
+#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */
+#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
+
+#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE _UL(0x00040000) /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */
+
+#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */
+#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */
+#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE _UL(0x10010300)
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J18A_H */
diff --git a/bootloader/lib/samd21/samd21a/include/system_samd21.h b/bootloader/lib/samd21/samd21a/include/system_samd21.h
new file mode 100644
index 0000000..223911c
--- /dev/null
+++ b/bootloader/lib/samd21/samd21a/include/system_samd21.h
@@ -0,0 +1,47 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ * a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SYSTEM_SAMD21_H_INCLUDED_
+#define _SYSTEM_SAMD21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAMD21_H_INCLUDED */
diff --git a/bootloader/lib/usb_msc/sbc_protocol.h b/bootloader/lib/usb_msc/sbc_protocol.h
new file mode 100644
index 0000000..f2b9be1
--- /dev/null
+++ b/bootloader/lib/usb_msc/sbc_protocol.h
@@ -0,0 +1,165 @@
+/**
+ * \file
+ *
+ * \brief SCSI Block Commands
+ *
+ * This file contains definitions of some of the commands found in the
+ * SCSI SBC-2 standard.
+ *
+ * Note that the SBC specification depends on several commands defined
+ * by the SCSI Primary Commands (SPC) standard. Each version of the SBC
+ * standard is meant to be used in conjunction with a specific version
+ * of the SPC standard, as follows:
+ * - SBC depends on SPC
+ * - SBC-2 depends on SPC-3
+ * - SBC-3 depends on SPC-4
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _SBC_PROTOCOL_H_
+#define _SBC_PROTOCOL_H_
+
+#include "lib/usb_msc/usb_includes.h"
+
+/**
+ * \ingroup usb_msc_protocol
+ * \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions
+ *
+ * @{
+ */
+
+/** \name SCSI commands defined by SBC-2 */
+#define SBC_FORMAT_UNIT 0x04
+#define SBC_READ6 0x08
+#define SBC_WRITE6 0x0A
+#define SBC_START_STOP_UNIT 0x1B
+#define SBC_READ_CAPACITY10 0x25
+#define SBC_READ10 0x28
+#define SBC_WRITE10 0x2A
+#define SBC_VERIFY10 0x2F
+
+/** \name SBC-2 Mode page definitions */
+enum scsi_sbc_mode {
+ SCSI_MS_MODE_RW_ERR_RECOV = 0x01, /**< Read-Write Error Recovery mode page */
+ SCSI_MS_MODE_FORMAT_DEVICE = 0x03, /**< Format Device mode page */
+ SCSI_MS_MODE_FLEXIBLE_DISK = 0x05, /**< Flexible Disk mode page */
+ SCSI_MS_MODE_CACHING = 0x08
+};
+
+/** \name SBC-2 Device-Specific Parameter */
+#define SCSI_MS_SBC_WP 0x80 /**< Write Protected */
+#define SCSI_MS_SBC_DPOFUA 0x10 /**< DPO and FUA supported */
+
+/**
+ * \brief SBC-2 Short LBA mode parameter block descriptor
+ * \note Fields are MSB first (BE)
+ */
+struct sbc_slba_block_desc {
+ be32_t nr_blocks; /**< Number of Blocks (BE32) */
+ be32_t block_len; /**< Block Length (BE32) */
+#define SBC_SLBA_BLOCK_LEN_MASK 0x00FFFFFFU /**< Mask reserved bits */
+};
+
+/**
+ * \brief SBC-2 Caching mode page
+ * \note Fields are MSB first (BE)
+ */
+struct sbc_caching_mode_page {
+ uint8_t page_code;
+ uint8_t page_length;
+ uint8_t flags2;
+#define SBC_MP_CACHE_IC (1 << 7) /**< Initiator Control */
+#define SBC_MP_CACHE_ABPF (1 << 6) /**< Abort Pre-Fetch */
+#define SBC_MP_CACHE_CAP (1 << 5) /**< Catching Analysis Permitted */
+#define SBC_MP_CACHE_DISC (1 << 4) /**< Discontinuity */
+#define SBC_MP_CACHE_SIZE (1 << 3) /**< Size enable */
+#define SBC_MP_CACHE_WCE (1 << 2) /**< Write back Cache Enable */
+#define SBC_MP_CACHE_MF (1 << 1) /**< Multiplication Factor */
+#define SBC_MP_CACHE_RCD (1 << 0) /**< Read Cache Disable */
+ uint8_t retention;
+ be16_t dis_pf_transfer_len;
+ be16_t min_prefetch;
+ be16_t max_prefetch;
+ be16_t max_prefetch_ceil;
+ uint8_t flags12;
+#define SBC_MP_CACHE_FSW (1 << 7) /**< Force Sequential Write */
+#define SBC_MP_CACHE_LBCSS (1 << 6) /**< Logical Blk Cache Seg Sz */
+#define SBC_MP_CACHE_DRA (1 << 5) /**< Disable Read-Ahead */
+#define SBC_MP_CACHE_NV_DIS (1 << 0) /**< Non-Volatile Cache Disable */
+ uint8_t nr_cache_segments;
+ be16_t cache_segment_size;
+ uint8_t reserved[4];
+};
+
+/**
+ * \brief SBC-2 Read-Write Error Recovery mode page
+ * \note Fields are MSB first (BE)
+ */
+struct sbc_rdwr_error_recovery_mode_page {
+ uint8_t page_code;
+ uint8_t page_length;
+#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A
+ uint8_t flags1;
+#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7)
+#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6)
+#define SBC_MP_RW_ERR_RECOV_TB (1 << 5)
+#define SBC_MP_RW_ERR_RECOV_RC (1 << 4)
+#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3)
+#define SBC_MP_RW_ERR_RECOV_PER (1 << 2)
+#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1)
+#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0)
+ uint8_t read_retry_count;
+ uint8_t correction_span;
+ uint8_t head_offset_count;
+ uint8_t data_strobe_offset_count;
+ uint8_t flags2;
+ uint8_t write_retry_count;
+ uint8_t flags3;
+ be16_t recovery_time_limit;
+};
+
+/**
+ * \brief SBC-2 READ CAPACITY (10) parameter data (8 bytes)
+ * \note Fields are MSB first (BE)
+ */
+struct sbc_read_capacity10_data {
+ be32_t max_lba; /**< LBA of last logical block (BE32) */
+ be32_t block_len; /**< Number of bytes in the last logical block (BE32) */
+};
+
+#endif /*_SBC_PROTOCOL_H_*/
diff --git a/bootloader/lib/usb_msc/spc_protocol.h b/bootloader/lib/usb_msc/spc_protocol.h
new file mode 100644
index 0000000..2a68216
--- /dev/null
+++ b/bootloader/lib/usb_msc/spc_protocol.h
@@ -0,0 +1,342 @@
+/**
+ * \file
+ *
+ * \brief SCSI Primary Commands
+ *
+ * This file contains definitions of some of the commands found in the
+ * SPC-2 standard.
+ *
+ * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _SPC_PROTOCOL_H_
+#define _SPC_PROTOCOL_H_
+
+#include "lib/usb_msc/usb_includes.h"
+
+/**
+ * \ingroup usb_msc_protocol
+ * \defgroup usb_spc_protocol SCSI Primary Commands protocol definitions
+ *
+ *
+ */
+
+/**< \name SCSI commands defined by SPC-2 */
+#define SPC_TEST_UNIT_READY 0x00
+#define SPC_REQUEST_SENSE 0x03
+#define SPC_INQUIRY 0x12
+#define SPC_MODE_SELECT6 0x15
+#define SPC_MODE_SENSE6 0x1A
+#define SPC_SEND_DIAGNOSTIC 0x1D
+#define SPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E
+#define SPC_MODE_SENSE10 0x5A
+#define SPC_REPORT_LUNS 0xA0
+
+/**< \brief May be set in byte 0 of the INQUIRY CDB */
+/**< Enable Vital Product Data */
+#define SCSI_INQ_REQ_EVPD 0x01
+/**< Command Support Data specified by the PAGE OR OPERATION CODE field */
+#define SCSI_INQ_REQ_CMDT 0x02
+
+_Pragma("pack(1)")
+
+/**
+ * \brief SCSI Standard Inquiry data structure
+ */
+struct scsi_inquiry_data {
+ uint8_t pq_pdt; /**< Peripheral Qual / Peripheral Dev Type */
+#define SCSI_INQ_PQ_CONNECTED 0x00 /**< Peripheral connected */
+#define SCSI_INQ_PQ_NOT_CONN 0x20 /**< Peripheral not connected */
+#define SCSI_INQ_PQ_NOT_SUPP 0x60 /**< Peripheral not supported */
+#define SCSI_INQ_DT_DIR_ACCESS 0x00 /**< Direct Access (SBC) */
+#define SCSI_INQ_DT_SEQ_ACCESS 0x01 /**< Sequential Access */
+#define SCSI_INQ_DT_PRINTER 0x02 /**< Printer */
+#define SCSI_INQ_DT_PROCESSOR 0x03 /**< Processor device */
+#define SCSI_INQ_DT_WRITE_ONCE 0x04 /**< Write-once device */
+#define SCSI_INQ_DT_CD_DVD 0x05 /**< CD/DVD device */
+#define SCSI_INQ_DT_OPTICAL 0x07 /**< Optical Memory */
+#define SCSI_INQ_DT_MC 0x08 /**< Medium Changer */
+#define SCSI_INQ_DT_ARRAY 0x0c /**< Storage Array Controller */
+#define SCSI_INQ_DT_ENCLOSURE 0x0d /**< Enclosure Services */
+#define SCSI_INQ_DT_RBC 0x0e /**< Simplified Direct Access */
+#define SCSI_INQ_DT_OCRW 0x0f /**< Optical card reader/writer */
+#define SCSI_INQ_DT_BCC 0x10 /**< Bridge Controller Commands */
+#define SCSI_INQ_DT_OSD 0x11 /**< Object-based Storage */
+#define SCSI_INQ_DT_NONE 0x1f /**< No Peripheral */
+ uint8_t flags1; /**< Flags (byte 1) */
+#define SCSI_INQ_RMB 0x80 /**< Removable Medium */
+ uint8_t version; /**< Version */
+#define SCSI_INQ_VER_NONE 0x00 /**< No standards conformance */
+#define SCSI_INQ_VER_SPC 0x03 /**< SCSI Primary Commands (link to SBC) */
+#define SCSI_INQ_VER_SPC2 0x04 /**< SCSI Primary Commands - 2 (link to SBC-2) */
+#define SCSI_INQ_VER_SPC3 0x05 /**< SCSI Primary Commands - 3 (link to SBC-2) */
+#define SCSI_INQ_VER_SPC4 0x06 /**< SCSI Primary Commands - 4 (link to SBC-3) */
+ uint8_t flags3; /**< Flags (byte 3) */
+#define SCSI_INQ_NORMACA 0x20 /**< Normal ACA Supported */
+#define SCSI_INQ_HISUP 0x10 /**< Hierarchal LUN addressing */
+#define SCSI_INQ_RSP_SPC2 0x02 /**< SPC-2 / SPC-3 response format */
+ uint8_t addl_len; /**< Additional Length (n-4) */
+#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) /**< Total length is \a tot */
+ uint8_t flags5; /**< Flags (byte 5) */
+#define SCSI_INQ_SCCS 0x80
+ uint8_t flags6; /**< Flags (byte 6) */
+#define SCSI_INQ_BQUE 0x80
+#define SCSI_INQ_ENCSERV 0x40
+#define SCSI_INQ_MULTIP 0x10
+#define SCSI_INQ_MCHGR 0x08
+#define SCSI_INQ_ADDR16 0x01
+ uint8_t flags7; /**< Flags (byte 7) */
+#define SCSI_INQ_WBUS16 0x20
+#define SCSI_INQ_SYNC 0x10
+#define SCSI_INQ_LINKED 0x08
+#define SCSI_INQ_CMDQUE 0x02
+ uint8_t vendor_id[8]; /**< T10 Vendor Identification */
+ uint8_t product_id[16]; /**< Product Identification */
+ uint8_t product_rev[4]; /**< Product Revision Level */
+};
+
+/**
+ * \brief SCSI Standard Request sense data structure
+ */
+#define SCSI_SENSE_VALID 0x80 /**< Indicates the INFORMATION field contains valid information */
+#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F
+#define SCSI_SENSE_CURRENT 0x70 /**< Response code 70h (current errors) */
+#define SCSI_SENSE_DEFERRED 0x71
+
+#define SCSI_SENSE_FILEMARK 0x80 /**< Indicates that the current command has read a filemark or setmark. */
+#define SCSI_SENSE_EOM 0x40 /**< Indicates that an end-of-medium condition exists. */
+#define SCSI_SENSE_ILI \
+ 0x20 /**< Indicates that the requested logical block length did not match the logical block length of the data on \
+ the medium. */
+#define SCSI_SENSE_RESERVED 0x10 /**< Reserved */
+#define SCSI_SENSE_KEY(x) (x & 0x0F) /**< Sense Key */
+
+#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len)-8)
+
+#define SCSI_SENSE_SKSV 0x80 /**< Indicates the SENSE-KEY SPECIFIC field contains valid information */
+
+struct scsi_request_sense_data {
+ /** 1st byte: REQUEST SENSE response flags*/
+ uint8_t valid_reponse_code;
+ /** 2nd byte */
+ uint8_t obsolete;
+ /** 3rd byte */
+ uint8_t sense_flag_key;
+ /** 4th to 7th bytes - INFORMATION field */
+ uint8_t information[4];
+ /** 8th byte - ADDITIONAL SENSE LENGTH field */
+ uint8_t AddSenseLen;
+ /** 9th to 12th byte - COMMAND-SPECIFIC INFORMATION field */
+ uint8_t CmdSpecINFO[4];
+ /** 13th to 14th byte - ADDITIONAL SENSE CODE and QUALIFIER field */
+ union {
+ struct {
+ uint8_t code; /**< ADDITIONAL SENSE CODE (ASC) */
+ uint8_t qualifier; /**< ADDITIONAL SENSE CODE QUALIFIER (ASCQ) */
+ } add_sense;
+ be16_t AddSense; /**< ASC | ASCQ */
+ };
+ /** 15th byte - FIELD REPLACEABLE UNIT CODE field */
+ uint8_t FldReplUnitCode;
+ /** 16th byte */
+ uint8_t SenseKeySpec[3];
+};
+
+_Pragma("pack()")
+
+/**< Vital Product Data page codes */
+enum scsi_vpd_page_code {
+ SCSI_VPD_SUPPORTED_PAGES = 0x00,
+ SCSI_VPD_UNIT_SERIAL_NUMBER = 0x80,
+ SCSI_VPD_DEVICE_IDENTIFICATION = 0x83
+};
+#define SCSI_VPD_HEADER_SIZE 4
+
+/**< Constants associated with the Device Identification VPD page */
+#define SCSI_VPD_ID_HEADER_SIZE 4
+
+#define SCSI_VPD_CODE_SET_BINARY 1
+#define SCSI_VPD_CODE_SET_ASCII 2
+#define SCSI_VPD_CODE_SET_UTF8 3
+
+#define SCSI_VPD_ID_TYPE_T10 1
+
+/**< Sense keys */
+enum scsi_sense_key {
+ SCSI_SK_NO_SENSE = 0x0,
+ SCSI_SK_RECOVERED_ERROR = 0x1,
+ SCSI_SK_NOT_READY = 0x2,
+ SCSI_SK_MEDIUM_ERROR = 0x3,
+ SCSI_SK_HARDWARE_ERROR = 0x4,
+ SCSI_SK_ILLEGAL_REQUEST = 0x5,
+ SCSI_SK_UNIT_ATTENTION = 0x6,
+ SCSI_SK_DATA_PROTECT = 0x7,
+ SCSI_SK_BLANK_CHECK = 0x8,
+ SCSI_SK_VENDOR_SPECIFIC = 0x9,
+ SCSI_SK_COPY_ABORTED = 0xa,
+ SCSI_SK_ABORTED_COMMAND = 0xb,
+ SCSI_SK_VOLUME_OVERFLOW = 0xd,
+ SCSI_SK_MISCOMPARE = 0xe
+};
+
+/**< Additional Sense Code | Additional Sense Code Qualifier pairs (BE16) */
+enum scsi_asc_ascq {
+ SCSI_ASC_NO_ADDITIONAL_SENSE_INFO = 0x0000,
+ SCSI_ASC_LU_NOT_READY_REBUILD_IN_PROGRESS = 0x0405,
+ SCSI_ASC_WRITE_ERROR = 0x0c00,
+ SCSI_ASC_UNRECOVERED_READ_ERROR = 0x1100,
+ SCSI_ASC_INVALID_COMMAND_OPERATION_CODE = 0x2000,
+ SCSI_ASC_INVALID_FIELD_IN_CDB = 0x2400,
+ SCSI_ASC_WRITE_PROTECTED = 0x2700,
+ SCSI_ASC_NOT_READY_TO_READY_CHANGE = 0x2800,
+ SCSI_ASC_MEDIUM_NOT_PRESENT = 0x3A00,
+ SCSI_ASC_INTERNAL_TARGET_FAILURE = 0x4400
+};
+
+/**
+ * \brief SPC-2 Mode parameter
+ * This subclauses describes the block descriptors and the pages
+ * used with MODE SELECT and MODE SENSE commands
+ * that are applicable to all SCSI devices.
+ */
+enum scsi_spc_mode {
+ SCSI_MS_MODE_VENDOR_SPEC = 0x00,
+ SCSI_MS_MODE_INFEXP = 0x1C, /**< Informational exceptions control page */
+ SCSI_MS_MODE_ALL = 0x3f
+};
+
+/**
+ * \brief SPC-2 Informational exceptions control page
+ * See chapter 8.3.8
+ * \note Fields are MSB first (BE)
+ */
+struct spc_control_page_info_execpt {
+ uint8_t page_code;
+ uint8_t page_length;
+#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A
+ uint8_t flags1;
+#define SPC_MP_INFEXP_PERF (1 << 7) /**< Initiator Control */
+#define SPC_MP_INFEXP_EBF (1 << 5) /**< Caching Analysis Permitted */
+#define SPC_MP_INFEXP_EWASC (1 << 4) /**< Discontinuity */
+#define SPC_MP_INFEXP_DEXCPT (1 << 3) /**< Size enable */
+#define SPC_MP_INFEXP_TEST (1 << 2) /**< Write-back Cache Enable */
+#define SPC_MP_INFEXP_LOGERR (1 << 0) /**< Log errors bit */
+ uint8_t mrie;
+#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00
+#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01
+#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02
+#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03
+#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04
+#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05
+#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06
+ be32_t interval_timer;
+ be32_t report_count;
+};
+
+enum scsi_spc_mode_sense_pc {
+ SCSI_MS_SENSE_PC_CURRENT = 0,
+ SCSI_MS_SENSE_PC_CHANGEABLE = 1,
+ SCSI_MS_SENSE_PC_DEFAULT = 2,
+ SCSI_MS_SENSE_PC_SAVED = 3
+};
+
+/**
+ * \brief Check whether dbd field is set in sense code
+ * \param[in] cdb pointer to the sense code block
+ * \return Operation status.
+ */
+static inline bool scsi_mode_sense_dbd_is_set(const uint8_t *cdb)
+{
+ return (cdb[1] >> 3) & 1;
+}
+
+/**
+ * \brief Get page code from mode sense code
+ * \param[in] cdb pointer to the sense code block
+ * \return Operation status.
+ */
+static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t *cdb)
+{
+ return cdb[2] & 0x3f;
+}
+
+/**
+ * \brief Get pc from mode sense code
+ * \param[in] cdb pointer to the sense code block
+ * \return Operation status.
+ */
+static inline uint8_t scsi_mode_sense_get_pc(const uint8_t *cdb)
+{
+ return cdb[2] >> 6;
+}
+
+/**
+ * \brief SCSI Mode Parameter Header used by MODE SELECT(6) and MODE SENSE(6)
+ * \note Fields are MSB first (BE)
+ */
+struct scsi_mode_param_header6 {
+ uint8_t mode_data_length; /**< Number of bytes after this */
+ uint8_t medium_type; /**< Medium Type */
+ uint8_t device_specific_parameter; /**< Defined by command set */
+ uint8_t block_descriptor_length; /**< Length of block descriptors */
+};
+
+/**
+ * \brief SCSI Mode Parameter Header used by MODE SELECT(10) and MODE SENSE(10)
+ * \note Fields are MSB first (BE)
+ */
+struct scsi_mode_param_header10 {
+ le16_t mode_data_length; /**< Number of bytes after this */
+ uint8_t medium_type; /**< Medium Type */
+ uint8_t device_specific_parameter; /**< Defined by command set */
+ uint8_t flags4; /**< LONGLBA in bit 0 */
+ uint8_t reserved;
+ le16_t block_descriptor_length; /**< Length of block descriptors */
+};
+
+/**
+ * \brief SCSI Page_0 Mode Page header (SPF not set)
+ */
+struct scsi_mode_page_0_header {
+ uint8_t page_code;
+#define SCSI_PAGE_CODE_PS (1 << 7) /**< Parameters Savable */
+#define SCSI_PAGE_CODE_SPF (1 << 6) /**< SubPage Format */
+ uint8_t page_length; /**< Number of bytes after this */
+#define SCSI_MS_PAGE_LEN(total) ((total)-2)
+};
+
+#endif /**< SPC_PROTOCOL_H_ */
diff --git a/bootloader/lib/usb_msc/usb_includes.h b/bootloader/lib/usb_msc/usb_includes.h
new file mode 100644
index 0000000..b41cd69
--- /dev/null
+++ b/bootloader/lib/usb_msc/usb_includes.h
@@ -0,0 +1,137 @@
+/**
+ * \file
+ *
+ * \brief USB Include Header Files.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved.
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+#ifndef _USB_INCLUDES_H_
+#define _USB_INCLUDES_H_
+
+#ifdef USB_USER_INCLUDES
+
+//#include "usb_user_includes.h"
+
+#else
+/* Include START headers */
+#include
+#include
+#include
+//#include
+//#include
+//#include
+//#include
+
+typedef uint16_t le16_t;
+typedef uint32_t le32_t;
+typedef uint16_t be16_t;
+typedef uint32_t be32_t;
+
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define is_constant(exp) __builtin_constant_p(exp)
+#else
+#define is_constant(exp) (0)
+#endif
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define swap_u16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) | ((uint16_t)(u16) << 8)))
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#if (defined __GNUC__)
+#define swap_u32(u32) \
+ (is_constant(u32) \
+ ? ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16))) \
+ : ((uint32_t)__builtin_bswap32((uint32_t)(u32))))
+#else
+#define swap_u32(u32) \
+ ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16)))
+#endif
+
+/** Get a value from/to LE16 data */
+#define LE16(x) (x)
+/** Get a value from/to LE32 data */
+#define LE32(x) (x)
+/** Get a value from/to BE16 data */
+#define BE16(x) swap_u16(x)
+/** Get a value from/to BE32 data */
+#define BE32(x) swap_u32(x)
+
+/** Get byte 0 for BE 16-bit value */
+#define BE16B0(a) ((uint8_t)((a) >> 8))
+/** Get byte 1 for BE 16-bit value */
+#define BE16B1(a) ((uint8_t)((a) >> 0))
+
+/** Get byte 0 for BE 32-bit value */
+#define BE32B0(a) ((uint8_t)((a) >> 24))
+/** Get byte 1 for BE 32-bit value */
+#define BE32B1(a) ((uint8_t)((a) >> 16))
+/** Get byte 2 for BE 32-bit value */
+#define BE32B2(a) ((uint8_t)((a) >> 8))
+/** Get byte 3 for BE 32-bit value */
+#define BE32B3(a) ((uint8_t)((a) >> 0))
+
+/** Get byte 0 for LE 16-bit value */
+#define LE16B0(a) ((uint8_t)((a) >> 0))
+/** Get byte 1 for LE 16-bit value */
+#define LE16B1(a) ((uint8_t)((a) >> 8))
+
+/** Get byte 0 for LE 32-bit value */
+#define LE32B0(a) ((uint8_t)((a) >> 0))
+/** Get byte 1 for LE 32-bit value */
+#define LE32B1(a) ((uint8_t)((a) >> 8))
+/** Get byte 2 for LE 32-bit value */
+#define LE32B2(a) ((uint8_t)((a) >> 16))
+/** Get byte 3 for LE 32-bit value */
+#define LE32B3(a) ((uint8_t)((a) >> 24))
+
+#endif /* USB_USER_INCLUDES */
+
+#endif /* _USB_INCLUDES_H_ */
diff --git a/bootloader/lib/usb_msc/usb_protocol.h b/bootloader/lib/usb_msc/usb_protocol.h
new file mode 100644
index 0000000..2ffa70a
--- /dev/null
+++ b/bootloader/lib/usb_msc/usb_protocol.h
@@ -0,0 +1,765 @@
+/**
+ * \file
+ *
+ * \brief USB protocol definitions.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (C) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+#ifndef _USB_PROTOCOL_H_
+#define _USB_PROTOCOL_H_
+
+#include "usb_includes.h"
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_protocol_group USB Protocol Definitions
+ *
+ * This module defines constants and data structures provided by the USB
+ * 2.0 specification.
+ *
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __CC_ARM
+#pragma anon_unions
+#endif
+
+/*! Value for field bcdUSB */
+#define USB_V2_0 (0x0200) /*!< USB Specification version 2.00 */
+#define USB_V2_1 (0x0201) /*!< USB Specification version 2.01 (support BOS) */
+
+/*! \name Generic definitions (Class, subclass and protocol)
+ */
+/*! @{ */
+#define USB_CLASS_NO (0x00)
+#define USB_SUBCLASS_NO (0x00)
+#define USB_PROTOCOL_NO (0x00)
+/*! @} */
+
+/*! \name IAD (Interface Association Descriptor) constants */
+/*! @{ */
+#define USB_CLASS_IAD (0xEF)
+#define USB_SUBCLASS_IAD (0x02)
+#define USB_PROTOCOL_IAD (0x01)
+/*! @} */
+
+/**
+ * \brief USB request data transfer direction (bmRequestType)
+ */
+#define USB_REQT_DIR_OUT (0 << 7) /*!< Host to device */
+#define USB_REQT_DIR_H2D (0 << 7) /*!< Host to device */
+#define USB_REQT_DIR_IN (1 << 7) /*!< Device to host */
+#define USB_REQT_DIR_D2H (1 << 7) /*!< Device to host */
+#define USB_REQT_DIR_MASK (1 << 7) /*!< Mask */
+
+/**
+ * \brief USB request types (bmRequestType)
+ */
+#define USB_REQT_TYPE_STANDARD (0 << 5) /*!< Standard request */
+#define USB_REQT_TYPE_CLASS (1 << 5) /*!< Class-specific request */
+#define USB_REQT_TYPE_VENDOR (2 << 5) /*!< Vendor-specific request */
+#define USB_REQT_TYPE_MASK (3 << 5) /*!< Mask */
+
+/**
+ * \brief USB recipient codes (bmRequestType)
+ */
+#define USB_REQT_RECIP_DEVICE (0 << 0) /*!< Recipient device */
+#define USB_REQT_RECIP_INTERFACE (1 << 0) /*!< Recipient interface */
+#define USB_REQT_RECIP_ENDPOINT (2 << 0) /*!< Recipient endpoint */
+#define USB_REQT_RECIP_OTHER (3 << 0) /*!< Recipient other */
+#define USB_REQT_RECIP_MASK (0x1F) /*!< Mask */
+
+/**
+ * \brief Standard USB control transfer stages.
+ */
+enum usb_ctrl_stage { USB_SETUP_STAGE = 0, USB_DATA_STAGE = 1, USB_STATUS_STAGE = 2 };
+
+/**
+ * \brief Standard USB requests (bRequest)
+ */
+enum usb_req_code {
+ USB_REQ_GET_STATUS = 0,
+ USB_REQ_CLEAR_FTR = 1,
+ USB_REQ_SET_FTR = 3,
+ USB_REQ_SET_ADDRESS = 5,
+ USB_REQ_GET_DESC = 6,
+ USB_REQ_SET_DESC = 7,
+ USB_REQ_GET_CONFIG = 8,
+ USB_REQ_SET_CONFIG = 9,
+ USB_REQ_GET_INTERFACE = 10,
+ USB_REQ_SET_INTERFACE = 11,
+ USB_REQ_SYNCH_FRAME = 12,
+ USB_REQ_SET_SEL = 48,
+ USB_REQ_ISOCH_DELAY = 49
+};
+
+/**
+ * \brief Standard USB device status flags
+ *
+ */
+enum usb_dev_status {
+ USB_DEV_STAT_BUS_POWERED = 0,
+ USB_DEV_STAT_SELF_POWERED = 1,
+ USB_DEV_STAT_REMOTEWAKEUP = 2,
+ USB_DEV_STAT_U1_ENABLE = 4,
+ USB_DEV_STAT_U2_ENABLE = 8,
+ USB_DEV_STAT_LTM_ENABLE = 16
+};
+
+/**
+ * \brief Standard USB Interface status flags
+ *
+ */
+enum usb_interface_status {
+ USB_IFACE_STAT_RESERVED = 0,
+ USB_IFACE_STAT_REMOTEWAKE_CAP = 1,
+ USB_IFACE_STAT_REMOTEWAKE = 2
+};
+
+/**
+ * \brief Standard USB endpoint status flags
+ *
+ */
+enum usb_endpoint_status { USB_EP_STAT_HALT = 1 };
+
+/**
+ * \brief Standard USB device feature flags
+ *
+ * \note valid for SetFeature request.
+ */
+enum usb_device_feature {
+ USB_DEV_FTR_REMOTE_WAKEUP = 1, /*!< Remote wakeup enabled */
+ USB_DEV_FTR_TEST_MODE = 2, /*!< USB test mode */
+ USB_DEV_FTR_OTG_B_HNP_ENABLE = 3,
+ USB_DEV_FTR_OTG_A_HNP_SP = 4,
+ USB_DEV_FTR_OTG_A_ALT_HNP_SP = 5,
+ USB_DEV_FTR_U1_ENABLE = 48,
+ USB_DEV_FTR_U2_ENABLE = 49,
+ USB_DEV_FTR_LTM_ENABLE = 50
+};
+
+/**
+ * \brief Test Mode possible on HS USB device
+ *
+ * \note valid for USB_DEV_FTR_TEST_MODE request.
+ */
+enum usb_device_hs_test_mode {
+ USB_DEV_TEST_MODE_J = 1,
+ USB_DEV_TEST_MODE_K = 2,
+ USB_DEV_TEST_MODE_SE0_NAK = 3,
+ USB_DEV_TEST_MODE_PACKET = 4,
+ USB_DEV_TEST_MODE_FORCE_ENABLE = 5
+};
+
+/**
+ * \brief Standard Feature Selectors for Interface
+ */
+enum usb_iface_feature { USB_IFACE_FTR_FUNC_SUSP = 0 };
+
+/**
+ * \brief Standard USB endpoint feature/status flags
+ */
+enum usb_endpoint_feature { USB_EP_FTR_HALT = 0 };
+
+/**
+ * \brief Standard USB Test Mode Selectors
+ */
+enum usb_test_mode_selector {
+ USB_TEST_J = 0x01,
+ USB_TEST_K = 0x02,
+ USB_TEST_SE0_NAK = 0x03,
+ USB_TEST_PACKET = 0x04,
+ USB_TEST_FORCE_ENABLE = 0x05
+};
+
+/**
+ * \brief Standard USB descriptor types
+ */
+enum usb_descriptor_type {
+ USB_DT_DEVICE = 1,
+ USB_DT_CONFIG = 2,
+ USB_DT_STRING = 3,
+ USB_DT_INTERFACE = 4,
+ USB_DT_ENDPOINT = 5,
+ USB_DT_DEVICE_QUALIFIER = 6,
+ USB_DT_OTHER_SPEED_CONFIG = 7,
+ USB_DT_INTERFACE_POWER = 8,
+ USB_DT_OTG = 9,
+ USB_DT_DEBUG = 10,
+ USB_DT_IAD = 11,
+ USB_DT_BOS = 15,
+ USB_DT_DEV_CAP = 16,
+ USB_DT_SS_EP_COMPANION = 48
+};
+
+/**
+ * \brief Capability types
+ */
+enum usb_capability_type {
+ USB_CAPT_WIRELESS = 1,
+ USB_CAPT_2_0_EXT = 2,
+ USB_CAPT_SUPER_SPEED = 3,
+ USB_CAPT_CONTAINER_ID = 4
+};
+
+/**
+ * \brief USB 2.0 Extension attributes
+ */
+enum usb_2_0_ext_attr { USB_2_0_EXT_LPM_SP = 1 };
+
+/**
+ * \brief USB SuperSpeed Capability attributes
+ */
+enum usb_ss_cap_attr { USB_SS_LTM_SP };
+
+/**
+ * \brief USB Speed Supports
+ */
+enum usb_speed_sp {
+ USB_SPEED_LOW_SP = 1,
+ USB_SPEED_LS_SP = 1,
+ USB_SPEED_FULL_SP = 2,
+ USB_SPEED_FS_SP = 2,
+ USB_SPEED_HIGH_SP = 4,
+ USB_SPEED_HS_SP = 4,
+ USB_SPEED_SUPER_SP = 8,
+ USB_SPEED_SS_SP = 8
+};
+
+/**
+ * \brief Standard USB endpoint transfer types
+ */
+enum usb_ep_type {
+ USB_EP_TYPE_CONTROL = 0x00,
+ USB_EP_TYPE_ISOCHRONOUS = 0x01,
+ USB_EP_TYPE_BULK = 0x02,
+ USB_EP_TYPE_INTERRUPT = 0x03,
+ USB_EP_TYPE_MASK = 0x03u
+};
+
+/**
+ * \brief USB endpoint interrupt types
+ */
+enum usb_ep_int_type { USB_EP_INT_T_PERIODIC = 0x00u, USB_EP_INT_T_NOTIFICATION = 0x01u, USB_EP_INT_T_MASK = 0x03u };
+
+/**
+ * \brief Standard USB endpoint synchronization types
+ */
+enum usb_ep_sync_type {
+ USB_EP_SYNC_T_NO = 0x00u,
+ USB_EP_SYNC_T_ASYNC = 0x02u,
+ USB_EP_SYNC_T_ADAPTIVE = 0x02u,
+ USB_EP_SYNC_T_SYNC = 0x03u,
+ USB_EP_SYNC_T_MASK = 0x03u
+};
+
+/**
+ * \brief Standard USB endpoint usage types
+ */
+enum usb_ep_usage_type {
+ USB_EP_USAGE_T_DATA = 0x00u,
+ USB_EP_USAGE_T_FEEDBACK = 0x01u,
+ USB_EP_USAGE_T_FEEDBACK_DATA = 0x02u,
+ USB_EP_USAGE_T_MASK = 0x03u
+};
+
+/**
+ * \brief Standard USB language IDs for string descriptors
+ */
+enum usb_langid {
+ USB_LANGID_EN_US = 0x0409 /*!< English (United States) */
+};
+
+/**
+ * \brief Mask selecting the index part of an endpoint address
+ */
+#define USB_EP_ADDR_MASK 0x0f
+/**
+ * \brief Endpoint transfer direction is IN
+ */
+#define USB_EP_DIR_IN 0x80
+/**
+ * \brief Endpoint transfer direction is OUT
+ */
+#define USB_EP_DIR_OUT 0x00
+
+/**
+ * \brief Maximum length in bytes of a USB descriptor
+ *
+ * The maximum length of a USB descriptor is limited by the 8-bit
+ * bLength field.
+ */
+#define USB_DESC_LEN_MAX 255
+
+/*
+ * 2-byte alignment requested for all USB structures.
+ */
+_Pragma("pack(1)")
+
+/**
+ * \brief A USB Device SETUP request
+ *
+ * The data payload of SETUP packets always follows this structure.
+ */
+typedef struct usb_req {
+ uint8_t bmRequestType;
+ uint8_t bRequest;
+ union {
+ le16_t wValue;
+ struct {
+ uint8_t l;
+ uint8_t h;
+ } wValueBytes;
+ };
+ union {
+ le16_t wIndex;
+ struct {
+ uint8_t l;
+ uint8_t h;
+ } wIndexBytes;
+ };
+ union {
+ le16_t wLength;
+ struct {
+ uint8_t l;
+ uint8_t h;
+ } wLengthBytes;
+ };
+} usb_req_t;
+
+/**
+ * \brief Standard USB device descriptor structure
+ */
+typedef struct usb_dev_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ le16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize0;
+ le16_t idVendor;
+ le16_t idProduct;
+ le16_t bcdDevice;
+ uint8_t iManufacturer;
+ uint8_t iProduct;
+ uint8_t iSerialNumber;
+ uint8_t bNumConfigurations;
+} usb_dev_desc_t;
+
+/**
+ * \brief Binary device Object Store (BOS) descriptor structure
+ */
+typedef struct usb_bos_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ le16_t wTotalLength;
+ uint8_t bNumDeviceCaps;
+} usb_bos_desc_t;
+
+/**
+ * \brief Device Capability Descriptor structure
+ */
+typedef struct usb_cap_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bDevCapabilityType;
+ uint8_t Vars[1];
+} usb_cap_desc_t;
+
+/**
+ * \brief USB 2.0 Extension Descriptor structure
+ */
+typedef struct usb_2_0_ext {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bDevCapabilityType;
+ uint32_t bmAttributes;
+} usb_2_0_ext_t;
+
+/**
+ * \brief LPM Device Capabilities descriptor structure
+ */
+typedef struct usb_2_0_ext usb_lpm_cap_desc_t;
+
+/**
+ * \brief SuperSpeed USB Device Capability structure
+ */
+typedef struct usb_ss_cap_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bDevCapabilityType;
+ uint8_t bmAttributes;
+ le16_t wSpeedsSupported;
+ uint8_t bFunctionalitySupport;
+ uint8_t bU1DevExitLat;
+ uint8_t bU2DevExitLat;
+} usb_ss_cap_desc_t;
+
+/**
+ * \brief USB Container ID Descriptor structure
+ */
+typedef struct usb_container_id_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bDevCapabilityType;
+ uint8_t bReserved;
+ uint8_t ContainerID[16];
+} usb_container_id_desc_t;
+
+/**
+ * \brief Standard USB device qualifier descriptor structure
+ *
+ * This descriptor contains information about the device when running at
+ * the "other" speed (i.e. if the device is currently operating at high
+ * speed, this descriptor can be used to determine what would change if
+ * the device was operating at full speed.)
+ */
+typedef struct usb_dev_qual_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ le16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize0;
+ uint8_t bNumConfigurations;
+ uint8_t bReserved;
+} usb_dev_qual_desc_t;
+
+/**
+ * \brief Standard USB configuration descriptor structure
+ */
+typedef struct usb_config_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ le16_t wTotalLength;
+ uint8_t bNumInterfaces;
+ uint8_t bConfigurationValue;
+ uint8_t iConfiguration;
+ uint8_t bmAttributes;
+ uint8_t bMaxPower;
+} usb_config_desc_t;
+
+#define USB_CONFIG_ATTR_MUST_SET (1 << 7) /*!< Must always be set */
+#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) /*!< Bus-powered */
+#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) /*!< Self-powered */
+#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) /*!< remote wakeup supported */
+
+#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) /*!< Max power in mA */
+
+/**
+ * \brief Standard USB association descriptor structure
+ */
+typedef struct usb_iad_desc {
+ uint8_t bLength; /*!< Size of this descriptor in bytes */
+ uint8_t bDescriptorType; /*!< Interface descriptor type */
+ uint8_t bFirstInterface; /*!< Number of interface */
+ uint8_t bInterfaceCount; /*!< value to select alternate setting */
+ uint8_t bFunctionClass; /*!< Class code assigned by the USB */
+ uint8_t bFunctionSubClass; /*!< Sub-class code assigned by the USB */
+ uint8_t bFunctionProtocol; /*!< Protocol code assigned by the USB */
+ uint8_t iFunction; /*!< Index of string descriptor */
+} usb_iad_desc_t;
+
+/**
+ * \brief Standard USB interface descriptor structure
+ */
+typedef struct usb_iface_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bInterfaceNumber;
+ uint8_t bAlternateSetting;
+ uint8_t bNumEndpoints;
+ uint8_t bInterfaceClass;
+ uint8_t bInterfaceSubClass;
+ uint8_t bInterfaceProtocol;
+ uint8_t iInterface;
+} usb_iface_desc_t;
+
+/**
+ * \brief Standard USB endpoint descriptor structure
+ */
+typedef struct usb_ep_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ le16_t wMaxPacketSize;
+ uint8_t bInterval;
+} usb_ep_desc_t;
+
+/**
+ * \brief SuperSpeed Endpoint Companion descriptor structure
+ */
+typedef struct usb_ss_ep_comp_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bMaxBurst;
+ uint8_t bmAttributes;
+ le16_t wBytesPerInterval;
+} usb_ss_ep_comp_desc_t;
+
+/**
+ * \brief LPM Token bmAttributes structure
+ */
+typedef struct usb_lpm_attributes {
+ uint8_t bLinkState : 4;
+ uint8_t HIRD : 4;
+ uint8_t bRemoteWake : 1;
+ uint8_t Reserved : 2;
+} usb_lpm_attributes_t;
+
+/**
+ * \brief A standard USB string descriptor structure
+ */
+typedef struct usb_str_desc {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+} usb_str_desc_t;
+
+typedef struct usb_str_langid_desc {
+ usb_str_desc_t desc;
+ le16_t string[1];
+} usb_str_langid_desc_t;
+
+_Pragma("pack()")
+
+/** \name Macros to build USB standard descriptors */
+/*@{*/
+
+/** Build bytes for USB device descriptor. */
+#define USB_DEV_DESC_BYTES(bcdUSB, \
+ bDeviceClass, \
+ bDeviceSubClass, \
+ bDeviceProtocol, \
+ bMaxPacketSize0, \
+ idVendor, \
+ idProduct, \
+ bcdDevice, \
+ iManufacturer, \
+ iProduct, \
+ iSerialNumber, \
+ bNumConfigurations) \
+ 18, /* bLength */ \
+ 0x01, /* bDescriptorType: DEVICE */ \
+ LE_BYTE0(bcdUSB), LE_BYTE1(bcdUSB), bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0, \
+ LE_BYTE0(idVendor), LE_BYTE1(idVendor), LE_BYTE0(idProduct), LE_BYTE1(idProduct), LE_BYTE0(bcdDevice), \
+ LE_BYTE1(bcdDevice), iManufacturer, iProduct, iSerialNumber, bNumConfigurations
+
+#define USB_DEV_DESC_LEN 18
+
+/** Build bytes for USB configuration descriptor. */
+#define USB_CONFIG_DESC_BYTES( \
+ wTotalLength, bNumInterfaces, bConfigurationValue, iConfiguration, bmAttributes, bMaxPower) \
+ 9, /* bLength */ \
+ 0x02, /* bDescriptorType: CONFIGURATION */ \
+ LE_BYTE0(wTotalLength), LE_BYTE1(wTotalLength), bNumInterfaces, bConfigurationValue, iConfiguration, \
+ bmAttributes, bMaxPower
+
+#define USB_CONFIG_DESC_LEN 9
+
+/** Build bytes for USB IAD descriptor. */
+#define USB_IAD_DESC_BYTES( \
+ bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction) \
+ 8, /* bLength */ \
+ USB_DT_IAD, /* bDescriptorType */ \
+ bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction
+
+#define USB_IAD_DESC_LEN 8
+
+/** Build bytes for USB interface descriptor. */
+#define USB_IFACE_DESC_BYTES(bInterfaceNumber, \
+ bAlternateSetting, \
+ bNumEndpoints, \
+ bInterfaceClass, \
+ bInterfaceSubClass, \
+ bInterfaceProtocol, \
+ iInterface) \
+ 9, /* bLength */ \
+ 0x04, /* bDescriptorType: INTERFACE */ \
+ bInterfaceNumber, bAlternateSetting, bNumEndpoints, bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, \
+ iInterface
+
+#define USB_IFACE_DESC_LEN 9
+
+/** Build bytes for USB endpoint descriptor. */
+#define USB_ENDP_DESC_BYTES(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \
+ 7, /* bLength */ \
+ 0x05, /* bDescriptorType: ENDPOINT */ \
+ bEndpointAddress, bmAttributes, LE_BYTE0(wMaxPacketSize), LE_BYTE1(wMaxPacketSize), bInterval
+
+#define USB_ENDP_DESC_LEN 7
+
+/*@}*/
+
+/** \brief Get a word (calculate by little endian 16-bit data)
+ * \param[in] ptr Byte pointer to the address to get data
+ * \return a 16-bit word
+ */
+static inline uint16_t usb_get_u16(const uint8_t *ptr)
+{
+ return (ptr[0] + (ptr[1] << 8));
+}
+
+/** \brief Get a double word (calculate by little endian 32-bit data)
+ * \param[in] ptr Byte pointer to the address to get data
+ * \return a 32-bit word
+ */
+static inline uint32_t usb_get_u32(const uint8_t *ptr)
+{
+ return (ptr[0] + (ptr[1] << 8) + (ptr[2] << 16) + (ptr[3] << 24));
+}
+
+/** \brief Get descriptor length
+ * \param[in] desc Byte pointer to the descriptor start address
+ * \return descriptor length
+ */
+static inline uint8_t usb_desc_len(const uint8_t *desc)
+{
+ return desc[0];
+}
+
+/** \brief Get descriptor type
+ * \param[in] desc Byte pointer to the descriptor start address
+ * \return descriptor type
+ */
+static inline uint8_t usb_desc_type(const uint8_t *desc)
+{
+ return desc[1];
+}
+
+/** \brief Get next USB descriptor
+ * \param[in] desc Byte pointer to the descriptor start address
+ * \return Byte pointer to the next descriptor
+ */
+static inline uint8_t *usb_desc_next(uint8_t *desc)
+{
+ return (desc + usb_desc_len(desc));
+}
+
+/** \brief Get idVendor of USB Device Descriptor
+ * \param[in] dev_desc Byte pointer to the descriptor start address
+ * \return 16-bit idVendor value
+ */
+static inline uint16_t usb_dev_desc_vid(const uint8_t *dev_desc)
+{
+ return usb_get_u16(dev_desc + 8);
+}
+
+/** \brief Get idProduct of USB Device Descriptor
+ * \param[in] dev_desc Byte pointer to the descriptor start address
+ * \return 16-bit idProduct value
+ */
+static inline uint16_t usb_dev_desc_pid(const uint8_t *dev_desc)
+{
+ return usb_get_u16(dev_desc + 10);
+}
+
+/** \brief Get wTotalLength of USB Configuration Descriptor
+ * \param[in] cfg_desc Byte pointer to the descriptor start address
+ * \return 16-bit total length of configuration list
+ */
+static inline uint16_t usb_cfg_desc_total_len(const uint8_t *cfg_desc)
+{
+ return usb_get_u16(cfg_desc + 2);
+}
+
+/** \brief Get Next USB Descriptor After the Configuration Descriptors list
+ * \param[in] cfg_desc Byte pointer to the descriptor start address
+ * \return Byte pointer to descriptor after configuration end
+ */
+static inline uint8_t *usb_cfg_desc_next(uint8_t *cfg_desc)
+{
+ return (cfg_desc + usb_cfg_desc_total_len(cfg_desc));
+}
+
+/** \brief Find specific USB Descriptor by its type
+ * \param[in] desc Byte pointer to the descriptor start address
+ * \param[in] eof Byte pointer to the descriptor end address
+ * \param[in] type The descriptor type expected
+ * \return Pointer to the descriptor
+ * \retval NULL if not found
+ */
+uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type);
+
+/** Get interface descriptor next to the specified one (by interface number)
+ * \param[in] desc Byte pointer to the descriptor start address
+ * \param[in] eof Byte pointer to the descriptor end address
+ * \param[in] iface_n The interface number to check
+ * \return Pointer to the descriptor
+ * \retval >= eof if not found
+ */
+uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n);
+
+/** Find endpoint descriptor, breaks if interface descriptor detected
+ * \param[in] desc Byte pointer to the descriptor start address
+ * \param[in] eof Byte pointer to the descriptor end address
+ * \return Pointer to the descriptor
+ * \retval NULL if not found
+ */
+uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof);
+
+/** Find configuration descriptor by its configuration number
+ * \param[in] desc Byte pointer to the descriptor start address
+ * \param[in] eof Byte pointer to the descriptor end address
+ * \param[in] cfg_value The configure value expected
+ * \return Pointer to the descriptor
+ * \retval NULL if not found
+ */
+uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value);
+
+/** Find string descriptor by its index
+ * \param[in] desc Byte pointer to the descriptor start address
+ * \param[in] eof Byte pointer to the descriptor end address
+ * \param[in] str_index The string index expected
+ * \return Pointer to the descriptor
+ * \retval NULL if not found
+ */
+uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @} */
+
+#endif /* _USB_PROTOCOL_H_ */
diff --git a/bootloader/lib/usb_msc/usb_protocol_msc.h b/bootloader/lib/usb_msc/usb_protocol_msc.h
new file mode 100644
index 0000000..ce304bf
--- /dev/null
+++ b/bootloader/lib/usb_msc/usb_protocol_msc.h
@@ -0,0 +1,177 @@
+/**
+ * \file
+ *
+ * \brief USB Mass Storage Class (MSC) protocol definitions.
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _USB_PROTOCOL_MSC_H_
+#define _USB_PROTOCOL_MSC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup usb_protocol_group
+ * \defgroup usb_msc_protocol USB Mass Storage Class (MSC) protocol definitions
+ *
+ * @{
+ */
+
+/**
+ * \name Possible Class value
+ */
+//@{
+#define MSC_CLASS 0x08
+//@}
+
+/**
+ * \name Possible SubClass value
+ * \note In practice, most devices should use
+ * #MSC_SUBCLASS_TRANSPARENT and specify the actual command set in
+ * the standard INQUIRY data block, even if the MSC spec indicates
+ * otherwise. In particular, RBC is not supported by certain major
+ * operating systems like Windows XP.
+ */
+//@{
+#define MSC_SUBCLASS_RBC 0x01 /**< Reduced Block Commands */
+#define MSC_SUBCLASS_ATAPI 0x02 /**< CD/DVD devices */
+#define MSC_SUBCLASS_QIC_157 0x03 /**< Tape devices */
+#define MSC_SUBCLASS_UFI 0x04 /**< Floppy disk drives */
+#define MSC_SUBCLASS_SFF_8070I 0x05 /**< Floppy disk drives */
+#define MSC_SUBCLASS_TRANSPARENT 0x06 /**< Determined by INQUIRY */
+ //@}
+
+/**
+ * \name Possible protocol value
+ * \note Only the BULK protocol should be used in new designs.
+ */
+//@{
+#define MSC_PROTOCOL_CBI 0x00 /**< Command/Bulk/Interrupt */
+#define MSC_PROTOCOL_CBI_ALT 0x01 /**< W/o command completion */
+#define MSC_PROTOCOL_BULK 0x50 /**< Bulk-only */
+ //@}
+
+/**
+ * \brief MSC USB requests (bRequest)
+ */
+
+#define USB_REQ_MSC_BULK_RESET 0xFF /**< Mass Storage Reset */
+#define USB_REQ_MSC_GET_MAX_LUN 0xFE /**< Get Max LUN */
+
+_Pragma("pack(1)")
+
+/**
+ * \name A Command Block Wrapper (CBW)
+ * \note Fields are LSB first (LE)
+ */
+//@{
+struct usb_msc_cbw {
+ le32_t dCBWSignature; /**< Must contain 'USBC' (0x43425355, LE32) */
+ le32_t dCBWTag; /**< Unique command ID (LE32) */
+ le32_t dCBWDataTransferLength; /**< Number of bytes to transfer (LE32) */
+ uint8_t bmCBWFlags; /**< Direction in bit 7 */
+ uint8_t bCBWLUN; /**< Logical Unit Number */
+ uint8_t bCBWCBLength; /**< Number of valid CDB bytes */
+ uint8_t CDB[16]; /**< SCSI Command Descriptor Block */
+};
+
+#define USB_CBW_SIGNATURE 0x43425355 /**< dCBWSignature value */
+#define USB_CBW_DIRECTION_IN (1 << 7) /**< Data from device to host */
+#define USB_CBW_DIRECTION_OUT (0 << 7) /**< Data from host to device */
+#define USB_CBW_LUN_MASK 0x0F /**< Valid bits in bCBWLUN */
+#define USB_CBW_LEN_MASK 0x1F /**< Valid bits in bCBWCBLength */
+ //@}
+
+/**
+ * \name A Command Status Wrapper (CSW)
+ * \note Fields are LSB first (LE)
+ */
+//@{
+struct usb_msc_csw {
+ le32_t dCSWSignature; /**< Must contain 'USBS' */
+ le32_t dCSWTag; /**< Same as dCBWTag */
+ le32_t dCSWDataResidue; /**< Number of bytes not transfered */
+ uint8_t bCSWStatus; /**< Status code */
+};
+
+#define USB_CSW_SIGNATURE 0x53425355 /**< dCSWSignature value */
+#define USB_CSW_STATUS_PASS 0x00 /**< Command Passed */
+#define USB_CSW_STATUS_FAIL 0x01 /**< Command Failed */
+#define USB_CSW_STATUS_PE 0x02 /**< Phase Error */
+//@}
+
+_Pragma("pack()")
+
+//@}
+
+/**
+ * \brief Fill a Bulk-Only Mass Storage Reset request
+ * \param[out] req Pointer to the request to fill
+ * \param[in] iface Interface Number
+ */
+static inline void usb_fill_BOMSReset_req(struct usb_req *req, uint8_t iface)
+{
+ req->bmRequestType = 0x21;
+ req->bRequest = USB_REQ_MSC_BULK_RESET;
+ req->wValue = 0;
+ req->wIndex = iface;
+ req->wLength = 0;
+}
+
+/**
+ * \brief Fill a GetMaxLUN request
+ * \param[out] req Pointer to the request to fill
+ * \param[in] iface Interface Number
+ */
+static inline void usb_fill_GetMaxLUN_req(struct usb_req *req, uint8_t iface)
+{
+ req->bmRequestType = 0xA1;
+ req->bRequest = USB_REQ_MSC_GET_MAX_LUN;
+ req->wValue = 0;
+ req->wIndex = iface;
+ req->wLength = 1;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _USB_PROTOCOL_MSC_H_
diff --git a/bootloader/platformio.ini b/bootloader/platformio.ini
new file mode 100644
index 0000000..2b76602
--- /dev/null
+++ b/bootloader/platformio.ini
@@ -0,0 +1,25 @@
+; VersaPad v2 -- UF2 bootloader
+; Vendored + adapted from Microsoft uf2-samdx1 (https://github.com/microsoft/uf2-samdx1),
+; trimmed to SAMD21 only, no self-update (SELF_EXECUTABLE) build, no Arduino framework.
+; Programmer: Atmel-ICE via SWD, same as the app firmware in ../platformio.ini.
+
+[env:versapad_bootloader]
+platform = atmelsam
+board = versapad_bootloader
+build_flags =
+ -D__SAMD21G17A__
+ -DSAMD21
+ -DCRYSTALLESS
+ -DFLASH_NUM_ROWS=512 ; ATSAMD21G17D: 128 KiB / 256 B rows (uf2.h defaults to 1024, the 256 KiB G18A value)
+ -I.
+ -Iinclude
+ -Iinc
+ -Ilib/cmsis/CMSIS/Include
+ -Ilib/samd21/samd21a/include
+ -Ilib/usb_msc
+
+board_build.ldscript = scripts/samd21g17a.ld
+
+upload_protocol = custom
+extra_scripts = ../upload_openocd.py
+debug_tool = openocd
diff --git a/bootloader/scripts/samd21g17a.ld b/bootloader/scripts/samd21g17a.ld
new file mode 100644
index 0000000..f3db0e6
--- /dev/null
+++ b/bootloader/scripts/samd21g17a.ld
@@ -0,0 +1,166 @@
+/**
+ * \file
+ *
+ * \brief Linker script for the UF2 bootloader on ATSAMD21G17D (128 KiB flash, 16 KiB RAM)
+ * Adapted from Microsoft uf2-samdx1 scripts/samd21j18a.ld
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00002000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* 16 KiB real RAM, not 32 KiB (G18A) */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ /*
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ */
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+
+ _binfo_start = 0x00002000 - 4 * 4;
+ .binfo _binfo_start : {
+ KEEP(*(.binfo)) ;
+ } > rom
+}
diff --git a/bootloader/src/cdc_enumerate.c b/bootloader/src/cdc_enumerate.c
new file mode 100644
index 0000000..3f18255
--- /dev/null
+++ b/bootloader/src/cdc_enumerate.c
@@ -0,0 +1,1152 @@
+/* ----------------------------------------------------------------------------
+ * SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "uf2.h"
+
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+PacketBuffer ctrlOutCache;
+PacketBuffer endpointCache[MAX_EP];
+
+__attribute__((__aligned__(4))) UsbDeviceDescriptor usb_endpoint_table[MAX_EP];
+
+__attribute__((__aligned__(4)))
+const char devDescriptor[] = {
+ /* Device descriptor */
+ 0x12, // bLength
+ 0x01, // bDescriptorType
+// bcdUSBL - v2.00; v2.10 is needed for WebUSB; there were issues with newer laptops running Win10
+// but it seems to be resolved
+#if USE_WEBUSB
+ 0x10,
+#else
+ 0x00,
+#endif
+ 0x02, //
+ 0xEF, // bDeviceClass: Misc
+ 0x02, // bDeviceSubclass:
+ 0x01, // bDeviceProtocol:
+ 0x40, // bMaxPacketSize0
+ USB_VID & 0xff, // vendor ID
+ USB_VID >> 8, //
+ USB_PID & 0xff, // product ID
+ USB_PID >> 8, //
+ 0x01, // bcdDeviceL
+ 0x42, //
+ 0x01, // iManufacturer // 0x01
+ 0x02, // iProduct
+ 0x03, // SerialNumber (required (!) for WebUSB)
+ 0x01 // bNumConfigs
+};
+
+#define CFG_DESC_SIZE (32 + USE_CDC * (58 + 8) + USE_HID * 32 + USE_WEBUSB * 23)
+#define HID_IF_NUM (USE_CDC ? 3 : 1)
+#define WEB_IF_NUM (HID_IF_NUM + 1)
+
+#if USE_HID
+// can be requested separately from the entire config desc
+__attribute__((__aligned__(4)))
+char hidCfgDescriptor[] = {
+ 9, // size
+ 4, // interface
+ HID_IF_NUM, // interface number
+ 0, // alternate
+ 2, // num. endpoints
+ 0x03, // HID
+ 0, // sub
+ 0, // sub
+ 3, // stringID
+};
+
+__attribute__((__aligned__(4)))
+const char hidDescriptor[] = {
+ 0x06, 0x97, 0xFF, // usage page vendor 0x97 (usage 0xff97 0x0001)
+ 0x09, 0x01, // usage 1
+ 0xA1, 0x01, // collection - application
+ 0x15, 0x00, // logical min 0
+ 0x26, 0xFF, 0x00, // logical max 255
+ 0x75, 8, // report size 8
+ 0x95, 64, // report count 64
+ 0x09, 0x01, // usage 1
+ 0x81, 0x02, // input: data, variable, absolute
+ 0x95, 64, // report count 64
+ 0x09, 0x01, // usage 1
+ 0x91, 0x02, // output: data, variable, absolute
+ 0x95, 1, // report count 1
+ 0x09, 0x01, // usage 1
+ 0xB1, 0x02, // feature: data, variable, absolute
+ 0xC0, // end
+};
+#endif
+
+#ifndef USB_POWER_MA
+#define USB_POWER_MA 500
+#endif
+__attribute__((__aligned__(4)))
+char cfgDescriptor[] = {
+ /* ============== CONFIGURATION 1 =========== */
+ /* Configuration 1 descriptor */
+ 0x09, // CbLength
+ 0x02, // CbDescriptorType
+ CFG_DESC_SIZE, // CwTotalLength 2 EP + Control
+ 0x00,
+ 1 + 2 * USE_CDC + USE_HID + USE_WEBUSB, // CbNumInterfaces
+ 0x01, // CbConfigurationValue
+ 0x00, // CiConfiguration
+ 0x80, // CbmAttributes 0x80 - bus-powered
+ USB_POWER_MA/2, // MaxPower (*2mA)
+
+#if USE_CDC
+ // IAD for CDC
+ 0x08, // bLength;
+ 0x0B, // bDescriptorType;
+ 0x00, // bFirstInterface;
+ 0x02, // bInterfaceCount;
+ 0x02, // bFunctionClass;
+ 0x02, // bFunctionSubclass;
+ 0x01, // bFunctionProtocol;
+ 0x00, // iFunction; string
+
+ /* Communication Class Interface Descriptor Requirement */
+ 0x09, // bLength
+ 0x04, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x01, // bNumEndpoints
+ 0x02, // bInterfaceClass
+ 0x02, // bInterfaceSubclass
+ 0x01, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ /* Header Functional Descriptor */
+ 0x05, // bFunction Length
+ 0x24, // bDescriptor type: CS_INTERFACE
+ 0x00, // bDescriptor subtype: Header Func Desc
+ 0x10, // bcdCDC:1.1
+ 0x01,
+
+ /* ACM Functional Descriptor */
+ 0x04, // bFunctionLength
+ 0x24, // bDescriptor Type: CS_INTERFACE
+ 0x02, // bDescriptor Subtype: ACM Func Desc
+ 0x06, // bmCapabilities
+
+ /* Union Functional Descriptor */
+ 0x05, // bFunctionLength
+ 0x24, // bDescriptorType: CS_INTERFACE
+ 0x06, // bDescriptor Subtype: Union Func Desc
+ 0x00, // bMasterInterface: Communication Class Interface
+ 0x01, // bSlaveInterface0: Data Class Interface
+
+ /* Call Management Functional Descriptor */
+ 0x05, // bFunctionLength
+ 0x24, // bDescriptor Type: CS_INTERFACE
+ 0x01, // bDescriptor Subtype: Call Management Func Desc
+ 0x03, // bmCapabilities: D1 + D0
+ 0x01, // bDataInterface: Data Class Interface 1
+
+ /* Endpoint 1 descriptor */
+ 0x07, // bLength
+ 0x05, // bDescriptorType
+ USB_EP_COMM | 0x80, // bEndpointAddress, Endpoint 03 - IN
+ 0x03, // bmAttributes INT
+ 0x08, // wMaxPacketSize
+ 0x00,
+ 0xFF, // bInterval
+
+ /* Data Class Interface Descriptor Requirement */
+ 0x09, // bLength
+ 0x04, // bDescriptorType
+ 0x01, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x02, // bNumEndpoints
+ 0x0A, // bInterfaceClass
+ 0x00, // bInterfaceSubclass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ /* First alternate setting */
+ /* Endpoint 1 descriptor */
+ 0x07, // bLength
+ 0x05, // bDescriptorType
+ USB_EP_IN | 0x80, // bEndpointAddress, Endpoint 01 - IN
+ 0x02, // bmAttributes BULK
+ PKT_SIZE, // wMaxPacketSize
+ 0x00,
+ 0x00, // bInterval
+
+ /* Endpoint 2 descriptor */
+ 0x07, // bLength
+ 0x05, // bDescriptorType
+ USB_EP_OUT, // bEndpointAddress, Endpoint 02 - OUT
+ 0x02, // bmAttributes BULK
+ PKT_SIZE, // wMaxPacketSize
+ 0x00,
+ 0x00, // bInterval
+#endif
+
+ // MSC
+
+ 9, /// descriptor size in bytes
+ 4, /// descriptor type - interface
+ USE_CDC ? 2 : 0, /// interface number
+ 0, /// alternate setting number
+ 2, /// number of endpoints
+ USE_MSC * 8, /// class code - mass storage
+ 6, /// subclass code - SCSI transparent command set
+ 80, /// protocol code - bulk only transport
+ 0, /// interface string index
+
+ 7, /// descriptor size in bytes
+ 5, /// descriptor type - endpoint
+ USB_EP_MSC_IN | 0x80, /// endpoint direction and number - in, 2
+ 2, /// transfer type - bulk
+ PKT_SIZE, /// maximum packet size
+ 0,
+ 0, /// not used
+
+ 7, /// descriptor size in bytes
+ 5, /// descriptor type - endpoint
+ USB_EP_MSC_OUT, /// endpoint direction and number - out, 1
+ 2, /// transfer type - bulk
+ PKT_SIZE, /// maximum packet size
+ 0,
+ 0, /// maximum NAK rate
+
+#if USE_HID
+ // HID
+ 9, // size
+ 4, // interface
+ HID_IF_NUM, // interface number
+ 0, // alternate
+ 2, // num. endpoints
+ 0x03, // HID
+ 0, // sub
+ 0, // sub
+ 0, // stringID
+
+ 9,
+ 0x21, // HID
+ 0x00, 0x01, // hidbcd 1.00
+ 0x00, // country code
+ 0x01, // num desc
+ 0x22, // report desc type
+ sizeof(hidDescriptor), 0, // size of report
+
+ // interrupt endpoints with interval=1
+ 7, 5, 0x80 | USB_EP_HID, 3, PKT_SIZE, 0, 1, // in
+ 7, 5, USB_EP_HID, 3, PKT_SIZE, 0, 1, // out
+#endif
+
+#if USE_WEBUSB
+ 9, // size
+ 4, // interface
+ WEB_IF_NUM, // interface number
+ 0, // alternate
+ 2, // num. endpoints
+ 0xFF, // Vendor
+ 42, // sub
+ 1, // sub
+ 0, // stringID
+
+ // interrupt endpoints with interval=1
+ 7, 5, 0x80 | USB_EP_WEB, 3, PKT_SIZE, 0, 1, // in
+ 7, 5, USB_EP_WEB, 3, PKT_SIZE, 0, 1, // out
+#endif
+};
+
+#define WINUSB_SIZE 170
+
+__attribute__((__aligned__(4)))
+static char bosDescriptor[] = {
+ 0x05, // Length
+ 0x0F, // Binary Object Store descriptor
+#if USE_WEBUSB
+ 0x39, 0x00, // Total length
+ 0x02, // Number of device capabilities
+#else
+ 0x05, 0x00, // Length
+ 0x00 // num caps
+#endif
+
+#if USE_WEBUSB
+ // WebUSB Platform Capability descriptor (bVendorCode == 0x01).
+ 0x18, // Length
+ 0x10, // Device Capability descriptor
+ 0x05, // Platform Capability descriptor
+ 0x00, // Reserved
+ 0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, // WebUSB GUID
+ 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65, // WebUSB GUID
+ 0x00, 0x01, // Version 1.0
+ 0x01, // Vendor request code
+ 0x00, // landing page
+
+ 0x1C, // Length
+ 0x10, // Device Capability descriptor
+ 0x05, // Platform Capability descriptor
+ 0x00, // Reserved
+ 0xDF, 0x60, 0xDD, 0xD8, 0x89, 0x45, 0xC7, 0x4C, // MS OS 2.0 GUID
+ 0x9C, 0xD2, 0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F, // MS OS 2.0 GUID
+ 0x00, 0x00, 0x03, 0x06, // Windows version
+ WINUSB_SIZE, 0x00, // Descriptor set length
+ 0x02, // Vendor request code
+ 0x00 // Alternate enumeration code
+#endif
+};
+
+#if USE_WEBUSB
+__attribute__((__aligned__(4)))
+static char msOS20Descriptor[] = {
+ // Microsoft OS 2.0 descriptor set header (table 10)
+ 0x0A, 0x00, // Descriptor size (10 bytes)
+ 0x00, 0x00, // MS OS 2.0 descriptor set header
+ 0x00, 0x00, 0x03, 0x06, // Windows version (8.1) (0x06030000)
+ WINUSB_SIZE, 0x00, // Size, MS OS 2.0 descriptor set
+
+ // Microsoft OS 2.0 function subset header
+ 0x08, 0x00, // Descriptor size (8 bytes)
+ 0x02, 0x00, // MS OS 2.0 function subset header
+ WEB_IF_NUM, // first interface no
+ 0x00, // Reserved
+ WINUSB_SIZE - 10, 0x00, // Size, MS OS 2.0 function subset
+
+ // Microsoft OS 2.0 compatible ID descriptor (table 13)
+ 20, 0x00, // wLength
+ 0x03, 0x00, // MS_OS_20_FEATURE_COMPATIBLE_ID
+ 'W', 'I', 'N', 'U', 'S', 'B', //
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ // interface guids
+ 132, 0, 4, 0, 7, 0,
+ //
+ 42, 0,
+ //
+ 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0,
+ 'a', 0, 'c', 0, 'e', 0, 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0,
+ //
+ 80, 0,
+ //
+ '{', 0, '9', 0, '2', 0, 'C', 0, 'E', 0, '6', 0, '4', 0, '6', 0, '2', 0, '-', 0, '9', 0, 'C', 0,
+ '7', 0, '7', 0, '-', 0, '4', 0, '6', 0, 'F', 0, 'E', 0, '-', 0, '9', 0, '3', 0, '3', 0, 'B', 0,
+ '-', 0, '3', 0, '1', 0, 'C', 0, 'B', 0, '9', 0, 'C', 0, '5', 0, 'B', 0, 'B', 0, '3', 0, 'B', 0,
+ '9', 0, '}', 0, 0, 0, 0, 0};
+
+STATIC_ASSERT(sizeof(msOS20Descriptor) == WINUSB_SIZE);
+
+#endif
+
+static uint8_t currentConfiguration;
+
+typedef struct {
+ uint8_t len;
+ uint8_t type;
+ uint8_t data[70];
+} StringDescriptor;
+
+
+// Serial numbers are derived from four 32-bit words. Add one character for null terminator
+#define SERIAL_NUMBER_LENGTH (4 * 8 + 1)
+// serial_number will be filled in when needed.
+static char serial_number[SERIAL_NUMBER_LENGTH];
+
+static const char *string_descriptors[] = {0, VENDOR_NAME, PRODUCT_NAME, serial_number};
+#define STRING_DESCRIPTOR_COUNT (sizeof(string_descriptors) / sizeof(string_descriptors[0]))
+
+static void load_serial_number(char serial_number[SERIAL_NUMBER_LENGTH]) {
+ // These are locations that taken together make up a unique serial number.
+ #ifdef SAMD21
+ uint32_t* addresses[4] = {(uint32_t *) 0x0080A00C, (uint32_t *) 0x0080A040,
+ (uint32_t *) 0x0080A044, (uint32_t *) 0x0080A048};
+ #endif
+ #ifdef SAMD51
+ uint32_t* addresses[4] = {(uint32_t *) 0x008061FC, (uint32_t *) 0x00806010,
+ (uint32_t *) 0x00806014, (uint32_t *) 0x00806018};
+ #endif
+ uint32_t serial_number_idx = 0;
+ for (int i = 0; i < 4; i++) {
+ serial_number_idx += writeNum(&(serial_number[serial_number_idx]), *(addresses[i]), true);
+ }
+ serial_number[serial_number_idx] = '\0';
+}
+
+#if USE_CDC
+static usb_cdc_line_coding_t line_coding = {
+ 115200, // baudrate
+ 0, // 1 Stop Bit
+ 0, // None Parity
+ 8 // 8 Data bits
+};
+
+static USB_CDC pCdc;
+#endif
+
+/* USB standard request code */
+#define STD_GET_STATUS_ZERO 0x0080
+#define STD_GET_STATUS_INTERFACE 0x0081
+#define STD_GET_STATUS_ENDPOINT 0x0082
+
+#define STD_CLEAR_FEATURE_ZERO 0x0100
+#define STD_CLEAR_FEATURE_INTERFACE 0x0101
+#define STD_CLEAR_FEATURE_ENDPOINT 0x0102
+#define STD_VENDOR_CTRL1 0x01C0
+#define STD_VENDOR_CTRL2 0x02C0
+
+#define STD_SET_FEATURE_ZERO 0x0300
+#define STD_SET_FEATURE_INTERFACE 0x0301
+#define STD_SET_FEATURE_ENDPOINT 0x0302
+
+#define STD_SET_ADDRESS 0x0500
+#define STD_GET_DESCRIPTOR 0x0680
+#define STD_GET_DESCRIPTOR1 0x0681
+#define STD_SET_DESCRIPTOR 0x0700
+#define STD_GET_CONFIGURATION 0x0880
+#define STD_SET_CONFIGURATION 0x0900
+#define STD_GET_INTERFACE 0x0A81
+#define STD_SET_INTERFACE 0x0B01
+#define STD_SYNCH_FRAME 0x0C82
+
+/* CDC Class Specific Request Code */
+#define GET_LINE_CODING 0x21A1
+#define SET_LINE_CODING 0x2021
+#define SET_CONTROL_LINE_STATE 0x2221
+
+// MSC
+#define MSC_RESET 0xFF21
+#define MSC_GET_MAX_LUN 0xFEA1
+
+// HID
+#define HID_REQUEST_GET_REPORT 0x01A1
+#define HID_REQUEST_GET_IDLE 0x02A1
+#define HID_REQUEST_GET_PROTOCOL 0x03A1
+#define HID_REQUEST_SET_REPORT 0x0921
+#define HID_REQUEST_SET_IDLE 0x0A21
+#define HID_REQUEST_SET_PROTOCOL 0x0B21
+
+static void AT91F_CDC_Enumerate(void);
+
+STATIC_ASSERT(sizeof(cfgDescriptor) == CFG_DESC_SIZE);
+
+/**
+ * \fn AT91F_InitUSB
+ *
+ * \brief Initializes USB
+ */
+void AT91F_InitUSB(void) {
+ uint32_t pad_transn, pad_transp, pad_trim;
+
+ /* Enable USB clock */
+ #ifdef SAMD21
+ PM->APBBMASK.reg |= PM_APBBMASK_USB;
+ #define DM_PIN PIN_PA24G_USB_DM
+ #define DM_MUX MUX_PA24G_USB_DM
+ #define DP_PIN PIN_PA25G_USB_DP
+ #define DP_MUX MUX_PA25G_USB_DP
+ #endif
+ #ifdef SAMD51
+ #define DM_PIN PIN_PA24H_USB_DM
+ #define DM_MUX MUX_PA24H_USB_DM
+ #define DP_PIN PIN_PA25H_USB_DP
+ #define DP_MUX MUX_PA25H_USB_DP
+ #endif
+
+ /* Set up the USB DP/DN pins */
+ PORT->Group[0].PINCFG[DM_PIN].bit.PMUXEN = 1;
+ PORT->Group[0].PMUX[DM_PIN / 2].reg &= ~(0xF << (4 * (DM_PIN & 0x01u)));
+ PORT->Group[0].PMUX[DM_PIN / 2].reg |= DM_MUX << (4 * (DM_PIN & 0x01u));
+ PORT->Group[0].PINCFG[DP_PIN].bit.PMUXEN = 1;
+ PORT->Group[0].PMUX[DP_PIN / 2].reg &= ~(0xF << (4 * (DP_PIN & 0x01u)));
+ PORT->Group[0].PMUX[DP_PIN / 2].reg |= DP_MUX << (4 * (DP_PIN & 0x01u));
+
+ #ifdef SAMD21
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(6) | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+ while (GCLK->STATUS.bit.SYNCBUSY) {}
+ #endif
+ #ifdef SAMD51
+ GCLK->PCHCTRL[USB_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+ MCLK->AHBMASK.bit.USB_ = true;
+ MCLK->APBBMASK.bit.USB_ = true;
+
+ while(GCLK->SYNCBUSY.bit.GENCTRL0) {}
+ #endif
+
+ /* Reset */
+ USB->HOST.CTRLA.bit.SWRST = 1;
+ while (USB->HOST.SYNCBUSY.bit.SWRST) {
+ /* Sync wait */
+ }
+
+ /* Load Pad Calibration */
+ pad_transn = ((*((uint32_t*) USB_FUSES_TRANSN_ADDR)) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
+
+ if (pad_transn == 0x1F) {
+ pad_transn = 5;
+ }
+
+ USB->HOST.PADCAL.bit.TRANSN = pad_transn;
+
+ pad_transp = ((*((uint32_t*) USB_FUSES_TRANSP_ADDR)) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
+
+ if (pad_transp == 0x1F) {
+ pad_transp = 29;
+ }
+
+ USB->HOST.PADCAL.bit.TRANSP = pad_transp;
+ pad_trim = ((*((uint32_t*) USB_FUSES_TRIM_ADDR)) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
+
+ if (pad_trim == 0x7) {
+ pad_trim = 3;
+ }
+
+ USB->HOST.PADCAL.bit.TRIM = pad_trim;
+
+ /* Set the configuration */
+ /* Set mode to Device mode */
+ USB->HOST.CTRLA.bit.MODE = 0;
+ /* Enable Run in Standby */
+ USB->HOST.CTRLA.bit.RUNSTDBY = true;
+ /* Set the descriptor address */
+ USB->HOST.DESCADD.reg = (uint32_t)(&usb_endpoint_table[0]);
+ /* Set speed configuration to Full speed */
+ USB->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val;
+ /* Attach to the USB host */
+ USB->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+
+ /* Initialize endpoint table RAM location to a known value 0 */
+ memset((uint8_t *)(&usb_endpoint_table[0]), 0, sizeof(usb_endpoint_table));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn USB_IsConfigured
+//* \brief Test if the device is configured and handle
+// enumerationDEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1
+//*----------------------------------------------------------------------------
+bool USB_Ok() {
+ timerTick();
+
+ /* Check for End of Reset flag */
+ if (USB->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) {
+ /* Clear the flag */
+ USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+ /* Set Device address as 0 */
+ USB->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | 0;
+ /* Configure endpoint 0 */
+ /* Configure Endpoint 0 for Control IN and Control OUT */
+ USB->DEVICE.DeviceEndpoint[0].EPCFG.reg =
+ USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
+ USB->DEVICE.DeviceEndpoint[0].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ USB->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ /* Configure control OUT Packet size to 64 bytes */
+ usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.SIZE = 3;
+ /* Configure control IN Packet size to 64 bytes */
+ usb_endpoint_table[0].DeviceDescBank[1].PCKSIZE.bit.SIZE = 3;
+ /* Configure the data buffer address for control OUT */
+ usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)&ctrlOutCache.buf;
+ /* Configure the data buffer address for control IN */
+ usb_endpoint_table[0].DeviceDescBank[1].ADDR.reg = (uint32_t)&endpointCache[0].buf;
+ /* Set Multipacket size to 8 for control OUT and byte count to 0*/
+ usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
+ usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+ USB->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+ // Reset current configuration value to 0
+ currentConfiguration = 0;
+ } else if (USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) {
+ AT91F_CDC_Enumerate();
+ }
+
+ return currentConfiguration != 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn USB_Read
+//* \brief Read available data from Endpoint OUT
+//*----------------------------------------------------------------------------
+uint32_t USB_ReadCore(void *pData, uint32_t length, uint32_t ep, PacketBuffer *cache) {
+ uint32_t packetSize = 0;
+ UsbDeviceDescriptor *epdesc = (UsbDeviceDescriptor *)USB->HOST.DESCADD.reg + ep;
+
+ if (!cache) {
+ cache = &endpointCache[ep];
+#if USE_HID || USE_WEBUSB
+ assert(ep != USB_EP_HID && ep != USB_EP_WEB);
+#endif
+ timerTick();
+ }
+
+ if (cache->ptr < cache->size) {
+ packetSize = MIN(cache->size - cache->ptr, length);
+ if (pData) {
+ memcpy(pData, cache->buf + cache->ptr, packetSize);
+ cache->ptr += packetSize;
+ }
+ return packetSize;
+ }
+
+ if (!cache->read_job) {
+ /* Set the buffer address for ep data */
+ epdesc->DeviceDescBank[0].ADDR.reg = (uint32_t)&cache->buf;
+ /* Set the byte count as zero */
+ epdesc->DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+ /* Set the byte count as zero */
+ epdesc->DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+ /* Start the reception by clearing the bank 0 ready bit */
+ USB->DEVICE.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = true;
+ /* set the user flag */
+ cache->read_job = true;
+ }
+
+ /* Check for Transfer Complete 0 flag */
+ if (USB->DEVICE.DeviceEndpoint[ep].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
+ /* Set packet size */
+ cache->size = epdesc->DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+
+ // this is when processing a hand-over
+ if (cache->read_job == 2) {
+ memcpy(&cache->buf, (void *)epdesc->DeviceDescBank[0].ADDR.reg, cache->size);
+ }
+
+ packetSize = MIN(cache->size, length);
+ if (pData) {
+ cache->ptr = packetSize;
+ /* Copy read data to user buffer */
+ memcpy(pData, cache->buf, packetSize);
+ } else {
+ cache->ptr = 0;
+ }
+ /* Clear the Transfer Complete 0 flag */
+ USB->DEVICE.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+ /* Clear the user flag */
+ cache->read_job = false;
+ }
+
+ // if (packetSize)
+ // logval("read", packetSize);
+
+ return packetSize;
+}
+
+uint32_t USB_Read(void *pData, uint32_t length, uint32_t ep) {
+ return USB_ReadCore(pData, length, ep, 0);
+}
+
+void USB_ReadBlocking(void *dst, uint32_t length, uint32_t ep, PacketBuffer *cache) {
+ /* Blocking read till specified number of bytes is received */
+ while (length) {
+ uint32_t curr = USB_ReadCore(dst, length, ep, cache);
+ // if (curr > 0)
+ // logval("readbl", length);
+ length -= curr;
+ dst = (char *)dst + curr;
+ }
+}
+
+uint32_t USB_Write(const void *pData, uint32_t length, uint8_t ep_num) {
+ return USB_WriteCore(pData, length, ep_num, false);
+}
+
+uint32_t USB_WriteCore(const void *pData, uint32_t length, uint8_t ep_num, bool handoverMode) {
+ uint32_t data_address;
+
+ UsbDeviceDescriptor *epdesc = (UsbDeviceDescriptor *)USB->HOST.DESCADD.reg + ep_num;
+
+ if (handoverMode) {
+ data_address = (uint32_t)pData;
+ epdesc->DeviceDescBank[1].PCKSIZE.bit.AUTO_ZLP = false;
+ }
+ /* Check for requirement for multi-packet or auto zlp */
+ else if (length >= (1 << (epdesc->DeviceDescBank[1].PCKSIZE.bit.SIZE + 3))) {
+ /* Update the EP data address */
+ data_address = (uint32_t)pData;
+ // data must be in RAM!
+ assert(data_address >= HMCRAMC0_ADDR);
+
+ // always disable AUTO_ZLP on MSC channel, otherwise enable
+ epdesc->DeviceDescBank[1].PCKSIZE.bit.AUTO_ZLP = ep_num == USB_EP_MSC_IN ? false : true;
+ } else {
+ /* Copy to local buffer */
+ memcpy(endpointCache[ep_num].buf, pData, length);
+ /* Update the EP data address */
+ data_address = (uint32_t)&endpointCache[ep_num].buf;
+ }
+
+ /* Set the buffer address for ep data */
+ epdesc->DeviceDescBank[1].ADDR.reg = data_address;
+ /* Set the byte count as zero */
+ epdesc->DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = length;
+ /* Set the multi packet size as zero for multi-packet transfers where length
+ * > ep size */
+ epdesc->DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+ /* Clear the transfer complete flag */
+ USB->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+ /* Set the bank as ready */
+ USB->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
+
+ /* Wait for transfer to complete */
+ while (!(USB->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)) {
+ // if (ep_num && !USB_Ok())
+ // return -1;
+ }
+
+ return length;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_USB_SendZlp
+//* \brief Send zero length packet through the control endpoint
+//*----------------------------------------------------------------------------
+void AT91F_USB_SendZlp(void) {
+ uint8_t c = 0;
+ USB_Write(&c, 0, 0);
+}
+
+static void configureInOut(uint8_t in_ep) {
+ /* Configure BULK OUT endpoint for CDC Data interface*/
+ USB->DEVICE.DeviceEndpoint[in_ep + 1].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(3);
+ /* Set maximum packet size as 64 bytes */
+ usb_endpoint_table[in_ep + 1].DeviceDescBank[0].PCKSIZE.bit.SIZE = 3;
+ USB->DEVICE.DeviceEndpoint[in_ep + 1].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ /* Configure the data buffer */
+ usb_endpoint_table[in_ep + 1].DeviceDescBank[0].ADDR.reg =
+ (uint32_t)&endpointCache[in_ep + 1].buf;
+
+ /* Configure BULK IN endpoint for CDC Data interface */
+ USB->DEVICE.DeviceEndpoint[in_ep].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE1(3);
+ /* Set maximum packet size as 64 bytes */
+ usb_endpoint_table[in_ep].DeviceDescBank[1].PCKSIZE.bit.SIZE = 3;
+ USB->DEVICE.DeviceEndpoint[in_ep].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ /* Configure the data buffer */
+ usb_endpoint_table[in_ep].DeviceDescBank[1].ADDR.reg = (uint32_t)&endpointCache[in_ep].buf;
+}
+
+static uint16_t wLength;
+
+static void sendCtrl(const void *data, uint32_t len) { USB_Write(data, MIN(len, wLength), 0); }
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CDC_Enumerate
+//* \brief This function is a callback invoked when a SETUP packet is received
+//*----------------------------------------------------------------------------
+void AT91F_CDC_Enumerate() {
+ uint8_t bmRequestType, bRequest, dir;
+ uint16_t wValue, wIndex, wStatus;
+
+ /* Clear the Received Setup flag */
+ USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+
+ /* Read the USB request parameters */
+ bmRequestType = ctrlOutCache.buf[0];
+ bRequest = ctrlOutCache.buf[1];
+ wValue = (ctrlOutCache.buf[2] & 0xFF);
+ wValue |= (ctrlOutCache.buf[3] << 8);
+ wIndex = (ctrlOutCache.buf[4] & 0xFF);
+ wIndex |= (ctrlOutCache.buf[5] << 8);
+ wLength = (ctrlOutCache.buf[6] & 0xFF);
+ wLength |= (ctrlOutCache.buf[7] << 8);
+
+ /* Clear the Bank 0 ready flag on Control OUT */
+ USB->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+ uint32_t reqId = (bRequest << 8) | bmRequestType;
+
+ logwrite("USBReq: ");
+ logwritenum(reqId);
+ logwrite(" wValue: ");
+ logwritenum(wValue);
+ logwrite(" wIndex: ");
+ logwritenum(wIndex);
+ logval(" wLen", wLength);
+
+ /* Handle supported standard device request Cf Table 9-3 in USB
+ * specification Rev 1.1 */
+ switch (reqId) {
+ case STD_GET_DESCRIPTOR1:
+ case STD_GET_DESCRIPTOR:
+ if (wValue == 0x100)
+ /* Return Device Descriptor */
+ sendCtrl(devDescriptor, sizeof(devDescriptor));
+ else if (wValue == 0x200)
+ /* Return Configuration Descriptor */
+ sendCtrl(cfgDescriptor, sizeof(cfgDescriptor));
+ else if (ctrlOutCache.buf[3] == 3) {
+ if (ctrlOutCache.buf[2] >= STRING_DESCRIPTOR_COUNT)
+ {
+ stall_ep(0);
+ } else {
+ StringDescriptor desc = {0};
+ desc.type = 3;
+ if (ctrlOutCache.buf[2] == 0) {
+ desc.len = 4;
+ desc.data[0] = 0x09;
+ desc.data[1] = 0x04;
+ } else {
+ load_serial_number(serial_number);
+ const char *ptr = string_descriptors[ctrlOutCache.buf[2]];
+ desc.len = strlen(ptr) * 2 + 2;
+ for (int i = 0; ptr[i]; i++) {
+ desc.data[i * 2] = ptr[i];
+ }
+ }
+ sendCtrl(&desc, desc.len);
+ }
+ } else if (ctrlOutCache.buf[3] == 0x0F) {
+ sendCtrl(bosDescriptor, sizeof(bosDescriptor));
+ }
+#if USE_HID
+ else if (ctrlOutCache.buf[3] == 0x21) {
+ sendCtrl(hidCfgDescriptor, sizeof(hidCfgDescriptor));
+ } else if (ctrlOutCache.buf[3] == 0x22) {
+ sendCtrl(hidDescriptor, sizeof(hidDescriptor));
+ }
+#endif
+ else {
+ /* Stall the request */
+ stall_ep(0);
+ }
+ break;
+#if USE_WEBUSB
+ case STD_VENDOR_CTRL1:
+ stall_ep(0);
+ break;
+ case STD_VENDOR_CTRL2:
+ if (wIndex == 0x07)
+ sendCtrl(msOS20Descriptor, sizeof(msOS20Descriptor));
+ else
+ stall_ep(0);
+ break;
+#endif
+ case STD_SET_ADDRESS:
+ /* Send ZLP */
+ AT91F_USB_SendZlp();
+ /* Set device address to the newly received address from host */
+ USB->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | wValue;
+ break;
+ case STD_SET_CONFIGURATION:
+ /* Store configuration */
+ currentConfiguration = (uint8_t)wValue;
+ /* Send ZLP */
+ AT91F_USB_SendZlp();
+
+#if USE_CDC
+ configureInOut(USB_EP_IN);
+
+ /* Configure INTERRUPT IN endpoint for CDC COMM interface*/
+ USB->DEVICE.DeviceEndpoint[USB_EP_COMM].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE1(4);
+ /* Set maximum packet size as 64 bytes */
+ usb_endpoint_table[USB_EP_COMM].DeviceDescBank[1].PCKSIZE.bit.SIZE = 0;
+ USB->DEVICE.DeviceEndpoint[USB_EP_COMM].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+#endif
+
+ configureInOut(USB_EP_MSC_IN);
+
+#if USE_HID
+ /* Configure INTERRUPT IN/OUT endpoint for HID interface*/
+ USB->DEVICE.DeviceEndpoint[USB_EP_HID].EPCFG.reg =
+ USB_DEVICE_EPCFG_EPTYPE0(4) | USB_DEVICE_EPCFG_EPTYPE1(4);
+
+ USB->DEVICE.DeviceEndpoint[USB_EP_HID].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ USB->DEVICE.DeviceEndpoint[USB_EP_HID].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ usb_endpoint_table[USB_EP_HID].DeviceDescBank[0].PCKSIZE.bit.SIZE = 3;
+ usb_endpoint_table[USB_EP_HID].DeviceDescBank[1].PCKSIZE.bit.SIZE = 3;
+#endif
+
+#if USE_WEBUSB
+ /* Configure INTERRUPT IN/OUT endpoint for HID interface*/
+ USB->DEVICE.DeviceEndpoint[USB_EP_WEB].EPCFG.reg =
+ USB_DEVICE_EPCFG_EPTYPE0(4) | USB_DEVICE_EPCFG_EPTYPE1(4);
+
+ USB->DEVICE.DeviceEndpoint[USB_EP_WEB].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ USB->DEVICE.DeviceEndpoint[USB_EP_WEB].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ usb_endpoint_table[USB_EP_WEB].DeviceDescBank[0].PCKSIZE.bit.SIZE = 3;
+ usb_endpoint_table[USB_EP_WEB].DeviceDescBank[1].PCKSIZE.bit.SIZE = 3;
+#endif
+
+ break;
+
+ case STD_GET_CONFIGURATION:
+ /* Return current configuration value */
+ sendCtrl(&(currentConfiguration), sizeof(currentConfiguration));
+ break;
+
+ case STD_GET_STATUS_ZERO:
+ wStatus = 0;
+ sendCtrl(&wStatus, sizeof(wStatus));
+ break;
+ case STD_GET_STATUS_INTERFACE:
+ wStatus = 0;
+ sendCtrl(&wStatus, sizeof(wStatus));
+ break;
+ case STD_GET_STATUS_ENDPOINT:
+ wStatus = 0;
+ dir = wIndex & 80;
+ wIndex &= 0x0F;
+ if (wIndex < MAX_EP) {
+ if (dir) {
+ wStatus = (USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUS.reg &
+ USB_DEVICE_EPSTATUSSET_STALLRQ1)
+ ? 1
+ : 0;
+ } else {
+ wStatus = (USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUS.reg &
+ USB_DEVICE_EPSTATUSSET_STALLRQ0)
+ ? 1
+ : 0;
+ }
+ /* Return current status of endpoint */
+ sendCtrl(&wStatus, sizeof(wStatus));
+ } else
+ /* Stall the request */
+ stall_ep(0);
+ break;
+ case STD_SET_FEATURE_ZERO:
+ /* Stall the request */
+ stall_ep(0);
+ break;
+ case STD_SET_FEATURE_INTERFACE:
+ /* Send ZLP */
+ AT91F_USB_SendZlp();
+ break;
+ case STD_SET_FEATURE_ENDPOINT:
+ dir = wIndex & 0x80;
+ wIndex &= 0x0F;
+ if ((wValue == 0) && wIndex && (wIndex < MAX_EP)) {
+ /* Set STALL request for the endpoint */
+ if (dir) {
+ USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSSET.reg =
+ USB_DEVICE_EPSTATUSSET_STALLRQ1;
+ } else {
+ USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSSET.reg =
+ USB_DEVICE_EPSTATUSSET_STALLRQ0;
+ }
+ /* Send ZLP */
+ AT91F_USB_SendZlp();
+ } else
+ /* Stall the request */
+ stall_ep(0);
+ break;
+ case STD_CLEAR_FEATURE_ZERO:
+ /* Stall the request */
+ stall_ep(0);
+ break;
+ case STD_CLEAR_FEATURE_INTERFACE:
+ /* Send ZLP */
+ AT91F_USB_SendZlp();
+ break;
+ case STD_CLEAR_FEATURE_ENDPOINT:
+ dir = wIndex & 0x80;
+ wIndex &= 0x0F;
+ if ((wValue == 0) && wIndex && (wIndex < MAX_EP)) {
+ if (dir) {
+ if (USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUS.reg &
+ USB_DEVICE_EPSTATUSSET_STALLRQ1) {
+ // Remove stall request
+ USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSCLR.reg =
+ USB_DEVICE_EPSTATUSCLR_STALLRQ1;
+ if (USB->DEVICE.DeviceEndpoint[wIndex].EPINTFLAG.reg &
+ USB_DEVICE_EPINTFLAG_STALL1) {
+ USB->DEVICE.DeviceEndpoint[wIndex].EPINTFLAG.reg =
+ USB_DEVICE_EPINTFLAG_STALL1;
+ // The Stall has occurred, then reset data toggle
+ USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSCLR.reg =
+ USB_DEVICE_EPSTATUSSET_DTGLIN;
+ }
+ }
+ } else {
+ if (USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUS.reg &
+ USB_DEVICE_EPSTATUSSET_STALLRQ0) {
+ // Remove stall request
+ USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSCLR.reg =
+ USB_DEVICE_EPSTATUSCLR_STALLRQ0;
+ if (USB->DEVICE.DeviceEndpoint[wIndex].EPINTFLAG.reg &
+ USB_DEVICE_EPINTFLAG_STALL0) {
+ USB->DEVICE.DeviceEndpoint[wIndex].EPINTFLAG.reg =
+ USB_DEVICE_EPINTFLAG_STALL0;
+ // The Stall has occurred, then reset data toggle
+ USB->DEVICE.DeviceEndpoint[wIndex].EPSTATUSCLR.reg =
+ USB_DEVICE_EPSTATUSSET_DTGLOUT;
+ }
+ }
+ }
+ /* Send ZLP */
+ AT91F_USB_SendZlp();
+ } else {
+ stall_ep(0);
+ }
+ break;
+
+#if USE_CDC
+ // handle CDC class requests
+ case SET_LINE_CODING:
+ /* Send ZLP */
+ AT91F_USB_SendZlp();
+ break;
+ case GET_LINE_CODING:
+ /* Send current line coding */
+ sendCtrl(&line_coding, sizeof(usb_cdc_line_coding_t));
+ break;
+ case SET_CONTROL_LINE_STATE:
+ /* Store the current connection */
+ pCdc.currentConnection = wValue;
+ /* Send ZLP */
+ AT91F_USB_SendZlp();
+ break;
+#endif
+
+#if USE_MSC_CHECKS
+ // MSC
+ case MSC_RESET:
+ DBG_MSC(logmsg("MSC reset"));
+ msc_reset();
+ break;
+#endif
+
+ case MSC_GET_MAX_LUN:
+ DBG_MSC(logmsg("MSC maxlun"));
+ wStatus = MAX_LUN;
+ sendCtrl(&wStatus, 1);
+ break;
+
+#if USE_HID
+ case HID_REQUEST_GET_PROTOCOL:
+ case HID_REQUEST_GET_IDLE:
+ case HID_REQUEST_GET_REPORT: {
+ uint8_t buf[8] = {0};
+ sendCtrl(buf, 8);
+ } break;
+
+ case HID_REQUEST_SET_IDLE:
+ case HID_REQUEST_SET_REPORT:
+ case HID_REQUEST_SET_PROTOCOL:
+ AT91F_USB_SendZlp();
+ break;
+#endif
+
+ default:
+ logval("Invalid CTRL command", reqId);
+ /* Stall the request */
+ stall_ep(0);
+ break;
+ }
+}
+
+static bool isInEP(uint8_t ep) { return ep == USB_EP_IN || ep == USB_EP_MSC_IN; }
+
+void reset_ep(uint8_t ep) {
+ assert(ep != 0);
+
+ // Stop transfer
+ if (isInEP(ep)) {
+ USB->DEVICE.DeviceEndpoint[ep].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+ // Eventually ack a transfer occur during abort
+ USB->DEVICE.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+ } else {
+ USB->DEVICE.DeviceEndpoint[ep].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+ // Eventually ack a transfer occur during abort
+ USB->DEVICE.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+ }
+}
+
+void stall_ep(uint8_t ep) {
+ logval("Stall EP", ep);
+ /* Check the direction */
+ if (ep == 0 || isInEP(ep)) {
+ /* Set STALL request on IN direction */
+ USB->DEVICE.DeviceEndpoint[ep].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
+ } else {
+ /* Set STALL request on OUT direction */
+ USB->DEVICE.DeviceEndpoint[ep].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
+ }
+}
+
+void usb_init(void) {
+ /* Initialize USB */
+ AT91F_InitUSB();
+ currentConfiguration = 0;
+#if USE_CDC
+ pCdc.currentConnection = 0;
+#endif
+ USB->HOST.CTRLA.bit.ENABLE = true;
+}
+
+#include "usart_sam_ba.h"
+
+#if USE_UART
+#define UART(e) \
+ if (b_sam_ba_interface_usart) \
+ return e;
+#else
+#define UART(e)
+#endif
+
+bool cdc_is_rx_ready(void) {
+ UART(usart_is_rx_ready())
+
+ /* Check whether the device is configured */
+ if (!USB_Ok())
+ return 0;
+
+ /* Return transfer complete 0 flag status */
+ return (USB->DEVICE.DeviceEndpoint[USB_EP_OUT].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0);
+}
+
+uint32_t cdc_write_buf(void const *data, uint32_t length) {
+ UART(usart_putdata(data, length))
+ /* Send the specified number of bytes on USB CDC */
+ USB_Write((const char *)data, length, USB_EP_IN);
+ return length;
+}
+
+uint32_t cdc_write_buf_xmd(void const *data, uint32_t length) {
+ UART(usart_putdata_xmd(data, length))
+ /* Send the specified number of bytes on USB CDC */
+ USB_Write((const char *)data, length, USB_EP_IN);
+ return length;
+}
+
+uint32_t cdc_read_buf(void *data, uint32_t length) {
+ UART(usart_getdata(data, length))
+
+ /* Check whether the device is configured */
+ if (!USB_Ok())
+ return 0;
+
+ /* Read from USB CDC */
+ return USB_Read((char *)data, length, USB_EP_OUT);
+}
+
+uint32_t cdc_read_buf_xmd(void *data, uint32_t length) {
+ UART(usart_getdata_xmd(data, length))
+ /* Check whether the device is configured */
+ if (!USB_Ok())
+ return 0;
+
+ /* Blocking read till specified number of bytes is received */
+ USB_ReadBlocking((char *)data, length, USB_EP_OUT, 0);
+
+ return length;
+}
diff --git a/bootloader/src/fat.c b/bootloader/src/fat.c
new file mode 100644
index 0000000..eb47666
--- /dev/null
+++ b/bootloader/src/fat.c
@@ -0,0 +1,262 @@
+
+#include "uf2.h"
+
+#define SERIAL0 (*(uint32_t *)0x0080A00C)
+#define SERIAL1 (*(uint32_t *)0x0080A040)
+#define SERIAL2 (*(uint32_t *)0x0080A044)
+#define SERIAL3 (*(uint32_t *)0x0080A048)
+
+typedef struct {
+ uint8_t JumpInstruction[3];
+ uint8_t OEMInfo[8];
+ uint16_t SectorSize;
+ uint8_t SectorsPerCluster;
+ uint16_t ReservedSectors;
+ uint8_t FATCopies;
+ uint16_t RootDirectoryEntries;
+ uint16_t TotalSectors16;
+ uint8_t MediaDescriptor;
+ uint16_t SectorsPerFAT;
+ uint16_t SectorsPerTrack;
+ uint16_t Heads;
+ uint32_t HiddenSectors;
+ uint32_t TotalSectors32;
+ uint8_t PhysicalDriveNum;
+ uint8_t Reserved;
+ uint8_t ExtendedBootSig;
+ uint32_t VolumeSerialNumber;
+ uint8_t VolumeLabel[11];
+ uint8_t FilesystemIdentifier[8];
+} __attribute__((packed)) FAT_BootBlock;
+
+typedef struct {
+ char name[8];
+ char ext[3];
+ uint8_t attrs;
+ uint8_t reserved;
+ uint8_t createTimeFine;
+ uint16_t createTime;
+ uint16_t createDate;
+ uint16_t lastAccessDate;
+ uint16_t highStartCluster;
+ uint16_t updateTime;
+ uint16_t updateDate;
+ uint16_t startCluster;
+ uint32_t size;
+} __attribute__((packed)) DirEntry;
+
+STATIC_ASSERT(sizeof(DirEntry) == 32);
+
+struct TextFile {
+ const char name[11];
+ const char *content;
+};
+
+#define STR0(x) #x
+#define STR(x) STR0(x)
+const char infoUf2File[] = //
+ "UF2 Bootloader " UF2_VERSION "\r\n"
+ "Model: " PRODUCT_NAME "\r\n"
+ "Board-ID: " BOARD_ID "\r\n";
+
+#if USE_FAT
+#if USE_INDEX_HTM
+const char indexFile[] = //
+ "\n"
+ ""
+ ""
+ ""
+ ""
+ "\n";
+#endif
+
+// WARNING -- code presumes only one NULL .content for .UF2 file
+// and requires it be the last element of the array
+static const struct TextFile info[] = {
+ {.name = "INFO_UF2TXT", .content = infoUf2File},
+#if USE_INDEX_HTM
+ {.name = "INDEX HTM", .content = indexFile},
+#endif
+ {.name = "CURRENT UF2"},
+};
+#define NUM_FILES (sizeof(info) / sizeof(info[0]))
+#define NUM_DIRENTRIES (NUM_FILES + 1) // Code adds volume label as first root directory entry
+
+#define UF2_SIZE (FLASH_SIZE * 2)
+#define UF2_SECTORS (UF2_SIZE / 512)
+#define UF2_FIRST_SECTOR (NUM_FILES + 1) // WARNING -- code presumes each non-UF2 file content fits in single sector
+#define UF2_LAST_SECTOR (UF2_FIRST_SECTOR + UF2_SECTORS - 1)
+#endif
+
+#define RESERVED_SECTORS 1
+#define ROOT_DIR_SECTORS 4
+#define SECTORS_PER_FAT ((NUM_FAT_BLOCKS * 2 + 511) / 512)
+
+#define START_FAT0 RESERVED_SECTORS
+#define START_FAT1 (START_FAT0 + SECTORS_PER_FAT)
+#define START_ROOTDIR (START_FAT1 + SECTORS_PER_FAT)
+#define START_CLUSTERS (START_ROOTDIR + ROOT_DIR_SECTORS)
+
+// all directory entries must fit in a single sector
+// because otherwise current code overflows buffer
+#define DIRENTRIES_PER_SECTOR (512/sizeof(DirEntry))
+#if USE_FAT
+STATIC_ASSERT(NUM_DIRENTRIES < DIRENTRIES_PER_SECTOR * ROOT_DIR_SECTORS);
+#endif
+
+static const FAT_BootBlock BootBlock = {
+ .JumpInstruction = {0xeb, 0x3c, 0x90},
+ .OEMInfo = "UF2 UF2 ",
+ .SectorSize = 512,
+ .SectorsPerCluster = 1,
+ .ReservedSectors = RESERVED_SECTORS,
+ .FATCopies = 2,
+ .RootDirectoryEntries = (ROOT_DIR_SECTORS * DIRENTRIES_PER_SECTOR),
+ .TotalSectors16 = NUM_FAT_BLOCKS - 2,
+ .MediaDescriptor = 0xf0, // typical for unpartitioned disks
+ .SectorsPerFAT = SECTORS_PER_FAT,
+ .SectorsPerTrack = 1,
+ .Heads = 1,
+ .PhysicalDriveNum = 0x00, // to match MediaDescriptor of 0xf0
+ .ExtendedBootSig = 0x29,
+ .VolumeSerialNumber = 0x00420042,
+ .VolumeLabel = VOLUME_LABEL,
+ .FilesystemIdentifier = "FAT16 ",
+};
+
+void padded_memcpy(char *dst, const char *src, int len) {
+ for (int i = 0; i < len; ++i) {
+ if (*src)
+ *dst = *src++;
+ else
+ *dst = ' ';
+ dst++;
+ }
+}
+
+void read_block(uint32_t block_no, uint8_t *data) {
+ memset(data, 0, 512);
+ uint32_t sectionIdx = block_no;
+
+ if (block_no == 0) { // Requested boot block
+ memcpy(data, &BootBlock, sizeof(BootBlock));
+ data[510] = 0x55;
+ data[511] = 0xaa;
+ // logval("data[0]", data[0]);
+ } else if (block_no < START_ROOTDIR) { // Requested FAT table sector
+ sectionIdx -= START_FAT0;
+ // logval("sidx", sectionIdx);
+ if (sectionIdx >= SECTORS_PER_FAT)
+ sectionIdx -= SECTORS_PER_FAT; // second FAT is same as the first...
+#if USE_FAT
+ if (sectionIdx == 0) {
+ data[0] = 0xf0; // must match MediaDescriptor
+ // WARNING -- code presumes only one NULL .content for .UF2 file
+ // and all non-NULL .content fit in one sector
+ // and requires it be the last element of the array
+ for (int i = 1; i < NUM_FILES * 2 + 4; ++i) {
+ data[i] = 0xff;
+ }
+ }
+ for (int i = 0; i < 256; ++i) { // Generate the FAT chain for the firmware "file"
+ uint32_t v = sectionIdx * 256 + i;
+ if (UF2_FIRST_SECTOR <= v && v <= UF2_LAST_SECTOR)
+ ((uint16_t *)(void *)data)[i] = v == UF2_LAST_SECTOR ? 0xffff : v + 1;
+ }
+#else
+ if (sectionIdx == 0)
+ memcpy(data, "\xf0\xff\xff\xff", 4);
+#endif
+ }
+#if USE_FAT
+ else if (block_no < START_CLUSTERS) { // Requested sector of the root directory
+ sectionIdx -= START_ROOTDIR;
+ if (sectionIdx == 0) {
+ DirEntry *d = (void *)data;
+ padded_memcpy(d->name, BootBlock.VolumeLabel, 11);
+ d->attrs = 0x28;
+ for (int i = 0; i < NUM_FILES; ++i) {
+ d++;
+ const struct TextFile *inf = &info[i];
+ d->size = inf->content ? strlen(inf->content) : UF2_SIZE;
+ d->startCluster = i + 2;
+ padded_memcpy(d->name, inf->name, 11);
+ d->createDate = 0x4d99;
+ d->updateDate = 0x4d99;
+ }
+ }
+ } else { // Requested sector from file space
+ sectionIdx -= START_CLUSTERS;
+ // WARNING -- code presumes all but last file take exactly one sector
+ if (sectionIdx < NUM_FILES - 1) {
+ memcpy(data, info[sectionIdx].content, strlen(info[sectionIdx].content));
+ } else {
+ sectionIdx -= NUM_FILES - 1;
+ uint32_t addr = sectionIdx * 256;
+ if (addr < FLASH_SIZE) {
+ UF2_Block *bl = (void *)data;
+ bl->magicStart0 = UF2_MAGIC_START0;
+ bl->magicStart1 = UF2_MAGIC_START1;
+ bl->magicEnd = UF2_MAGIC_END;
+ bl->blockNo = sectionIdx;
+ bl->numBlocks = FLASH_SIZE / 256;
+ bl->targetAddr = addr;
+ bl->payloadSize = 256;
+ bl->flags |= UF2_FLAG_FAMILYID_PRESENT;
+ bl->familyID = UF2_FAMILY;
+ memcpy(bl->data, (void *)addr, bl->payloadSize);
+ }
+ }
+ }
+#endif
+}
+
+void write_block(uint32_t block_no, uint8_t *data, bool quiet, WriteState *state) {
+ UF2_Block *bl = (void *)data;
+ if (!is_uf2_block(bl) || !UF2_IS_MY_FAMILY(bl)) {
+ return;
+ }
+
+ if ((bl->flags & UF2_FLAG_NOFLASH) || bl->payloadSize != 256 || (bl->targetAddr & 0xff) ||
+ bl->targetAddr < APP_START_ADDRESS || bl->targetAddr >= FLASH_SIZE) {
+#if USE_DBG_MSC
+ if (!quiet)
+ logval("invalid target addr", bl->targetAddr);
+#endif
+ // this happens when we're trying to re-flash CURRENT.UF2 file previously
+ // copied from a device; we still want to count these blocks to reset properly
+ } else {
+ // logval("write block at", bl->targetAddr);
+ flash_write_row((void *)bl->targetAddr, (void *)bl->data);
+ }
+
+ if (state && bl->numBlocks) {
+ if (state->numBlocks != bl->numBlocks) {
+ if (bl->numBlocks >= MAX_BLOCKS || state->numBlocks)
+ state->numBlocks = 0xffffffff;
+ else
+ state->numBlocks = bl->numBlocks;
+ }
+ if (bl->blockNo < MAX_BLOCKS) {
+ uint8_t mask = 1 << (bl->blockNo % 8);
+ uint32_t pos = bl->blockNo / 8;
+ if (!(state->writtenMask[pos] & mask)) {
+ // logval("incr", state->numWritten);
+ state->writtenMask[pos] |= mask;
+ state->numWritten++;
+ }
+ if (state->numWritten >= state->numBlocks) {
+ // wait a little bit before resetting, to avoid Windows transmit error
+ // https://github.com/Microsoft/uf2-samd21/issues/11
+ if (!quiet)
+ resetHorizon = timerHigh + 30;
+ // resetIntoApp();
+ }
+ }
+ } else {
+ if (!quiet)
+ resetHorizon = timerHigh + 300;
+ }
+}
diff --git a/bootloader/src/flash_samd21.c b/bootloader/src/flash_samd21.c
new file mode 100644
index 0000000..04348ac
--- /dev/null
+++ b/bootloader/src/flash_samd21.c
@@ -0,0 +1,115 @@
+#include "uf2.h"
+
+// this actually generates less code than a function
+#define wait_ready() \
+ while (NVMCTRL->INTFLAG.bit.READY == 0) \
+ ;
+
+void flash_erase_row(uint32_t *dst) {
+ wait_ready();
+ NVMCTRL->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+ // Execute "ER" Erase Row
+ NVMCTRL->ADDR.reg = (uint32_t)dst / 2;
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
+ wait_ready();
+}
+
+void flash_erase_to_end(uint32_t *start_address) {
+ // Note: the flash memory is erased in ROWS, that is in
+ // block of 4 pages.
+ // Even if the starting address is the last byte
+ // of a ROW the entire
+ // ROW is erased anyway.
+
+ uint32_t dst_addr = (uint32_t) start_address; // starting address
+
+ while (dst_addr < FLASH_SIZE) {
+ flash_erase_row((void *)dst_addr);
+ dst_addr += FLASH_ROW_SIZE;
+ }
+}
+
+void copy_words(uint32_t *dst, uint32_t *src, uint32_t n_words) {
+ while (n_words--)
+ *dst++ = *src++;
+}
+
+void flash_write_words(uint32_t *dst, uint32_t *src, uint32_t n_words) {
+ // Set automatic page write
+ NVMCTRL->CTRLB.bit.MANW = 0;
+
+ while (n_words > 0) {
+ uint32_t len = (FLASH_PAGE_SIZE >> 2) < n_words ? (FLASH_PAGE_SIZE >> 2) : n_words;
+ n_words -= len;
+
+ // Execute "PBC" Page Buffer Clear
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC;
+ wait_ready();
+
+ // make sure there are no other memory writes here
+ // otherwise we get lock-ups
+
+ while (len--)
+ *dst++ = *src++;
+
+ // Execute "WP" Write Page
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP;
+ wait_ready();
+ }
+}
+
+void flash_write(void) {
+ uint32_t *src = (void *)0x20006000;
+ uint32_t *dst = (void *)*src++;
+ uint32_t n_rows = *src++;
+
+ NVMCTRL->CTRLB.bit.MANW = 1;
+ while (n_rows--) {
+ wait_ready();
+ NVMCTRL->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+ // Execute "ER" Erase Row
+ NVMCTRL->ADDR.reg = (uint32_t)dst / 2;
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
+ wait_ready();
+
+ // there are 4 pages to a row
+ for (int i = 0; i < 4; ++i) {
+ // Execute "PBC" Page Buffer Clear
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC;
+ wait_ready();
+
+ uint32_t len = FLASH_PAGE_SIZE >> 2;
+ while (len--)
+ *dst++ = *src++;
+
+ // Execute "WP" Write Page
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP;
+ wait_ready();
+ }
+ }
+}
+
+// Skip writing blocks that are identical to the existing block.
+// only disable for debugging/timing
+#define QUICK_FLASH 1
+
+void flash_write_row(uint32_t *dst, uint32_t *src) {
+#if QUICK_FLASH
+ bool src_different = false;
+ for (int i = 0; i < FLASH_ROW_SIZE / 4; ++i) {
+ if (src[i] != dst[i]) {
+ src_different = true;
+ break;
+ }
+ }
+
+ if (!src_different) {
+ return;
+ }
+#endif
+
+ flash_erase_row(dst);
+ flash_write_words(dst, src, FLASH_ROW_SIZE / 4);
+}
diff --git a/bootloader/src/hid.c b/bootloader/src/hid.c
new file mode 100644
index 0000000..9ba8c53
--- /dev/null
+++ b/bootloader/src/hid.c
@@ -0,0 +1,220 @@
+#include "uf2.h"
+
+#if USE_HID || USE_WEBUSB
+
+typedef struct {
+ PacketBuffer pbuf;
+ uint16_t size;
+ uint8_t serial;
+ uint8_t ep;
+ union {
+ uint8_t buf[FLASH_ROW_SIZE + 64];
+ uint32_t buf32[(FLASH_ROW_SIZE + 64) / 4];
+ uint16_t buf16[(FLASH_ROW_SIZE + 64) / 2];
+ HF2_Command cmd;
+ HF2_Response resp;
+ };
+} HID_InBuffer;
+
+// Recieve HF2 message
+// Does not block. Will store intermediate data in pkt.
+// `serial` flag is cleared if we got a command message.
+int recv_hf2(HID_InBuffer *pkt) {
+ if (!USB_ReadCore(NULL, 64, pkt->ep, &pkt->pbuf))
+ return 0; // no data
+
+ // logval("rhf2", pkt->pbuf.size);
+ assert(pkt->pbuf.ptr == 0 && pkt->pbuf.size > 0);
+ pkt->pbuf.size = 0;
+ uint8_t tag = pkt->pbuf.buf[0];
+#if !USE_HID_SERIAL
+ if (tag & 0x80) {
+ return 0;
+ }
+#endif
+ // serial packets not allowed when in middle of command packet
+ assert(pkt->size == 0 || !(tag & HF2_FLAG_SERIAL_OUT));
+ memcpy(pkt->buf + pkt->size, pkt->pbuf.buf + 1, tag & HF2_SIZE_MASK);
+ pkt->size += tag & HF2_SIZE_MASK;
+ assert(pkt->size <= sizeof(pkt->buf));
+ tag &= HF2_FLAG_MASK;
+ if (tag != HF2_FLAG_CMDPKT_BODY) {
+#if USE_HID_SERIAL
+ pkt->serial = tag - 0x40;
+#endif
+ int sz = pkt->size;
+ pkt->size = 0;
+ return sz;
+ }
+ return 0;
+}
+
+// Send HF2 message.
+// Use command message when flag == HF2_FLAG_CMDPKT_BODY
+// Use serial stdout for HF2_FLAG_SERIAL_OUT and stderr for HF2_FLAG_SERIAL_ERR.
+void send_hf2(const void *data, int size, int ep, int flag) {
+ uint8_t buf[64];
+ const uint8_t *ptr = data;
+
+ for (;;) {
+ int s = 63;
+ if (size <= 63) {
+ s = size;
+ if (flag == HF2_FLAG_CMDPKT_BODY)
+ flag = HF2_FLAG_CMDPKT_LAST;
+ }
+ buf[0] = flag | s;
+ memcpy(buf + 1, ptr, s);
+ USB_WriteCore(buf, sizeof(buf), ep, true);
+ ptr += s;
+ size -= s;
+ if (!size)
+ break;
+ }
+}
+
+void send_hf2_response(HID_InBuffer *pkt, int size) {
+ logval("sendresp", size);
+ send_hf2(pkt->buf, 4 + size, pkt->ep, HF2_FLAG_CMDPKT_BODY);
+}
+
+static void checksum_pages(HID_InBuffer *pkt, int start, int num) {
+ for (int i = 0; i < num; ++i) {
+ uint8_t *data = (uint8_t *)start + i * FLASH_ROW_SIZE;
+ uint16_t crc = 0;
+ for (int j = 0; j < FLASH_ROW_SIZE; ++j) {
+ crc = add_crc(*data++, crc);
+ }
+ pkt->resp.data16[i] = crc;
+ }
+ send_hf2_response(pkt, num * 2);
+}
+
+void process_core(HID_InBuffer *pkt) {
+ int sz = recv_hf2(pkt);
+
+ if (!sz)
+ return;
+
+ uint32_t tmp;
+
+#if USE_HID_SERIAL
+ if (pkt->serial) {
+#if USE_LOGS
+ if (pkt->buf[0] == 'L') {
+ send_hf2(logStoreUF2.buffer, logStoreUF2.ptr, pkt->ep, HF2_FLAG_SERIAL_OUT);
+ } else
+#endif
+ {
+ send_hf2("OK\n", 3, pkt->ep, HF2_FLAG_SERIAL_ERR);
+ }
+ return;
+ }
+#endif
+
+ logwrite("HID sz=");
+ logwritenum(sz);
+ logval(" CMD", pkt->buf32[0]);
+
+ // one has to be careful dealing with these, as they share memory
+ HF2_Command *cmd = &pkt->cmd;
+ HF2_Response *resp = &pkt->resp;
+
+ uint32_t cmdId = cmd->command_id;
+ resp->tag = cmd->tag;
+ resp->status16 = HF2_STATUS_OK;
+
+#define checkDataSize(str, add) assert(sz == 8 + sizeof(cmd->str) + (add))
+
+ switch (cmdId) {
+ case HF2_CMD_INFO:
+ tmp = strlen(infoUf2File);
+ memcpy(pkt->resp.data8, infoUf2File, tmp);
+ send_hf2_response(pkt, tmp);
+ return;
+
+ case HF2_CMD_BININFO:
+ resp->bininfo.mode = HF2_MODE_BOOTLOADER;
+ resp->bininfo.flash_page_size = FLASH_ROW_SIZE;
+ resp->bininfo.flash_num_pages = FLASH_SIZE / FLASH_ROW_SIZE;
+ resp->bininfo.max_message_size = sizeof(pkt->buf);
+ resp->bininfo.uf2_family = UF2_FAMILY;
+ send_hf2_response(pkt, sizeof(resp->bininfo));
+ return;
+
+ case HF2_CMD_RESET_INTO_APP:
+ resetIntoApp();
+ break;
+ case HF2_CMD_RESET_INTO_BOOTLOADER:
+ resetIntoBootloader();
+ break;
+ case HF2_CMD_START_FLASH:
+ // userspace app should reboot into bootloader on this command; we just ignore it
+ // userspace can also call hf2_handover() here
+ break;
+ case HF2_CMD_WRITE_FLASH_PAGE:
+ checkDataSize(write_flash_page, FLASH_ROW_SIZE);
+ // first send ACK and then start writing, while getting the next packet
+ send_hf2_response(pkt, 0);
+ if (cmd->write_flash_page.target_addr >= APP_START_ADDRESS) {
+ flash_write_row((void *)cmd->write_flash_page.target_addr, cmd->write_flash_page.data);
+ }
+ return;
+#if USE_HID_EXT
+ case HF2_CMD_WRITE_WORDS:
+ checkDataSize(write_words, cmd->write_words.num_words << 2);
+ copy_words((void *)cmd->write_words.target_addr, cmd->write_words.words,
+ cmd->write_words.num_words);
+ break;
+ case HF2_CMD_READ_WORDS:
+ checkDataSize(read_words, 0);
+ tmp = cmd->read_words.num_words;
+ copy_words(resp->data32, (void *)cmd->read_words.target_addr, tmp);
+ send_hf2_response(pkt, tmp << 2);
+ return;
+#endif
+ case HF2_CMD_CHKSUM_PAGES:
+ checkDataSize(chksum_pages, 0);
+ checksum_pages(pkt, cmd->chksum_pages.target_addr, cmd->chksum_pages.num_pages);
+ return;
+
+ default:
+ // command not understood
+ resp->status16 = HF2_STATUS_INVALID_CMD;
+ break;
+ }
+
+ send_hf2_response(pkt, 0);
+}
+
+#if USE_HID
+static HID_InBuffer hidbufData;
+#endif
+
+#if USE_WEBUSB
+static HID_InBuffer webbufData;
+#endif
+
+void process_hid() {
+#if USE_HID
+ hidbufData.ep = USB_EP_HID;
+ process_core(&hidbufData);
+#endif
+#if USE_WEBUSB
+ webbufData.ep = USB_EP_WEB;
+ process_core(&webbufData);
+#endif
+}
+
+#if USE_HID_HANDOVER
+void hidHandoverLoop(int ep) {
+ handoverPrep();
+ HID_InBuffer buf = {0};
+ buf.ep = ep;
+ while (1) {
+ process_core(&buf);
+ }
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bootloader/src/images.c b/bootloader/src/images.c
new file mode 100644
index 0000000..ad25a81
--- /dev/null
+++ b/bootloader/src/images.c
@@ -0,0 +1,118 @@
+#include
+
+// all https://makecode.com/_VrfEKzV4xfvq
+
+// https://makecode.com/_7VxXm3JMPXfM - file
+// https://makecode.com/_LuEUCsPEKUbs - download
+const uint8_t fileLogo[] = {
+32, 32, 71, 140, 201, 151, 1, 2, 146, 1, 2, 146, 63, 2, 151, 9, 153, 9, 153, 9, 146, 1, 9, 146, 3, 9, 146, 7, 9, 137, 205, 72, 140, 206, 36, 139, 207, 18, 138, 206, 36, 139, 205, 72, 149, 7, 9, 146, 3, 9, 146, 1, 9, 153, 9, 153, 9, 153, 9, 148, 63, 2, 146, 1, 2, 146, 1, 2, 146, 201, 191, 191, 191, 174
+};
+
+// https://makecode.com/_9b0RcK5yRa12
+const uint8_t pendriveLogo[] = {
+32, 32, 59, 137, 215, 137, 1, 143, 1, 8, 146, 203, 149, 3, 8, 146, 3, 8, 146, 115, 8, 146, 115, 8, 146, 3, 8, 146, 3, 8, 146, 115, 8, 146, 115, 8, 146, 3, 8, 146, 3, 8, 146, 203, 149, 1, 8, 146, 1, 8, 146, 1, 120, 211, 191, 191, 191, 191, 191, 191, 191, 135
+};
+
+// https://makecode.com/_TTqbj705L4mr
+const uint8_t arrowLogo[] = {
+32, 32, 54, 137, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 151, 201, 146, 211, 142, 209, 144, 207, 146, 205, 148, 203, 150, 201, 152, 199, 154, 31, 154, 7, 154, 1, 191, 191, 191, 175
+};
+
+const uint8_t font8[] = {
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x5e, 0x00, 0x00, 0x00,
+0x00, 0x0e, 0x00, 0x0e, 0x00, 0x00,
+0x28, 0xfe, 0x28, 0xfe, 0x28, 0x00,
+0x4c, 0x92, 0xff, 0x92, 0x64, 0x00,
+0x02, 0x65, 0x12, 0x48, 0xa6, 0x40,
+0x6c, 0x92, 0x92, 0x6c, 0xa0, 0x00,
+0x00, 0x00, 0x0e, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x7c, 0x82, 0x00, 0x00,
+0x00, 0x00, 0x82, 0x7c, 0x00, 0x00,
+0x54, 0x38, 0x10, 0x38, 0x54, 0x00,
+0x10, 0x10, 0x7c, 0x10, 0x10, 0x00,
+0x00, 0x00, 0x90, 0x70, 0x00, 0x00,
+0x10, 0x10, 0x10, 0x10, 0x10, 0x00,
+0x00, 0x00, 0x60, 0x60, 0x00, 0x00,
+0x00, 0x60, 0x10, 0x08, 0x06, 0x00,
+0x00, 0x3c, 0x42, 0x42, 0x3c, 0x00,
+0x00, 0x44, 0x7e, 0x40, 0x00, 0x00,
+0x00, 0x44, 0x62, 0x52, 0x4c, 0x00,
+0x00, 0x42, 0x4a, 0x4e, 0x32, 0x00,
+0x30, 0x28, 0x24, 0x7e, 0x20, 0x00,
+0x00, 0x4e, 0x4a, 0x4a, 0x32, 0x00,
+0x00, 0x3c, 0x4a, 0x4a, 0x30, 0x00,
+0x00, 0x02, 0x62, 0x12, 0x0e, 0x00,
+0x00, 0x34, 0x4a, 0x4a, 0x34, 0x00,
+0x00, 0x0c, 0x52, 0x52, 0x3c, 0x00,
+0x00, 0x00, 0x6c, 0x6c, 0x00, 0x00,
+0x00, 0x00, 0x96, 0x76, 0x00, 0x00,
+0x10, 0x28, 0x28, 0x44, 0x44, 0x00,
+0x28, 0x28, 0x28, 0x28, 0x28, 0x00,
+0x44, 0x44, 0x28, 0x28, 0x10, 0x00,
+0x00, 0x02, 0x59, 0x09, 0x06, 0x00,
+0x3c, 0x42, 0x5a, 0x56, 0x08, 0x00,
+0x78, 0x14, 0x12, 0x14, 0x78, 0x00,
+0x7e, 0x4a, 0x4a, 0x4a, 0x34, 0x00,
+0x00, 0x3c, 0x42, 0x42, 0x24, 0x00,
+0x00, 0x7e, 0x42, 0x42, 0x3c, 0x00,
+0x00, 0x7e, 0x4a, 0x4a, 0x42, 0x00,
+0x00, 0x7e, 0x0a, 0x0a, 0x02, 0x00,
+0x00, 0x3c, 0x42, 0x52, 0x34, 0x00,
+0x00, 0x7e, 0x08, 0x08, 0x7e, 0x00,
+0x00, 0x42, 0x7e, 0x42, 0x00, 0x00,
+0x20, 0x40, 0x42, 0x3e, 0x02, 0x00,
+0x00, 0x7e, 0x08, 0x14, 0x62, 0x00,
+0x00, 0x7e, 0x40, 0x40, 0x40, 0x00,
+0x7e, 0x04, 0x18, 0x04, 0x7e, 0x00,
+0x00, 0x7e, 0x04, 0x08, 0x7e, 0x00,
+0x3c, 0x42, 0x42, 0x42, 0x3c, 0x00,
+0x00, 0x7e, 0x12, 0x12, 0x0c, 0x00,
+0x00, 0x3c, 0x52, 0x62, 0xbc, 0x00,
+0x00, 0x7e, 0x12, 0x12, 0x6c, 0x00,
+0x00, 0x24, 0x4a, 0x52, 0x24, 0x00,
+0x02, 0x02, 0x7e, 0x02, 0x02, 0x00,
+0x00, 0x3e, 0x40, 0x40, 0x3e, 0x00,
+0x00, 0x1e, 0x70, 0x70, 0x1e, 0x00,
+0x7e, 0x20, 0x18, 0x20, 0x7e, 0x00,
+0x42, 0x24, 0x18, 0x24, 0x42, 0x00,
+0x06, 0x08, 0x70, 0x08, 0x06, 0x00,
+0x00, 0x62, 0x52, 0x4a, 0x46, 0x00,
+0x00, 0x7e, 0x42, 0x42, 0x00, 0x00,
+0x00, 0x06, 0x08, 0x10, 0x60, 0x00,
+0x00, 0x42, 0x42, 0x7e, 0x00, 0x00,
+0x08, 0x04, 0x02, 0x04, 0x08, 0x00,
+0x80, 0x80, 0x80, 0x80, 0x80, 0x00,
+0x00, 0x00, 0x02, 0x04, 0x00, 0x00,
+0x00, 0x30, 0x48, 0x48, 0x78, 0x00,
+0x00, 0x7e, 0x48, 0x48, 0x30, 0x00,
+0x00, 0x30, 0x48, 0x48, 0x48, 0x00,
+0x00, 0x30, 0x48, 0x48, 0x7e, 0x00,
+0x00, 0x30, 0x68, 0x58, 0x50, 0x00,
+0x00, 0x10, 0x7c, 0x12, 0x04, 0x00,
+0x00, 0x18, 0xa4, 0xa4, 0x78, 0x00,
+0x00, 0x7e, 0x08, 0x08, 0x70, 0x00,
+0x00, 0x48, 0x7a, 0x40, 0x00, 0x00,
+0x00, 0x40, 0x84, 0x7d, 0x00, 0x00,
+0x00, 0x7e, 0x10, 0x28, 0x40, 0x00,
+0x00, 0x42, 0x7e, 0x40, 0x00, 0x00,
+0x78, 0x08, 0x30, 0x08, 0x70, 0x00,
+0x00, 0x78, 0x08, 0x08, 0x70, 0x00,
+0x00, 0x30, 0x48, 0x48, 0x30, 0x00,
+0x00, 0xfc, 0x24, 0x24, 0x18, 0x00,
+0x00, 0x18, 0x24, 0x24, 0xfc, 0x00,
+0x00, 0x78, 0x10, 0x08, 0x10, 0x00,
+0x00, 0x50, 0x58, 0x68, 0x28, 0x00,
+0x00, 0x08, 0x3e, 0x48, 0x20, 0x00,
+0x00, 0x38, 0x40, 0x40, 0x78, 0x00,
+0x00, 0x18, 0x60, 0x60, 0x18, 0x00,
+0x38, 0x40, 0x30, 0x40, 0x38, 0x00,
+0x00, 0x48, 0x30, 0x30, 0x48, 0x00,
+0x00, 0x5c, 0xa0, 0xa0, 0x7c, 0x00,
+0x00, 0x48, 0x68, 0x58, 0x48, 0x00,
+0x00, 0x08, 0x36, 0x41, 0x00, 0x00,
+0x00, 0x00, 0xfe, 0x00, 0x00, 0x00,
+0x00, 0x41, 0x36, 0x08, 0x00, 0x00,
+0x00, 0x08, 0x04, 0x08, 0x04, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
diff --git a/bootloader/src/init_samd21.c b/bootloader/src/init_samd21.c
new file mode 100644
index 0000000..e8b7431
--- /dev/null
+++ b/bootloader/src/init_samd21.c
@@ -0,0 +1,130 @@
+#include "uf2.h"
+#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6
+#define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR
+#define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos
+#define SYSCTRL_FUSES_OSC32K_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_Pos)
+
+volatile bool g_interrupt_enabled = true;
+
+static void gclk_sync(void) {
+ while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY)
+ ;
+}
+
+static void dfll_sync(void) {
+ while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0)
+ ;
+}
+
+#define NVM_SW_CALIB_DFLL48M_COARSE_VAL 58
+#define NVM_SW_CALIB_DFLL48M_FINE_VAL 64
+
+
+void system_init(void) {
+
+ NVMCTRL->CTRLB.bit.RWS = 1;
+
+#if defined(CRYSTALLESS)
+ /* Configure OSC8M as source for GCLK_GEN 2 */
+ GCLK->GENDIV.reg = GCLK_GENDIV_ID(2); // Read GENERATOR_ID - GCLK_GEN_2
+ gclk_sync();
+
+ GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_SRC_OSC8M_Val | GCLK_GENCTRL_GENEN;
+ gclk_sync();
+
+ // Turn on DFLL with USB correction and sync to internal 8 mhz oscillator
+ SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
+ dfll_sync();
+
+ SYSCTRL_DFLLVAL_Type dfllval_conf = {0};
+ uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_SW_CALIB_DFLL48M_COARSE_VAL / 32))
+ >> (NVM_SW_CALIB_DFLL48M_COARSE_VAL % 32))
+ & ((1 << 6) - 1);
+ if (coarse == 0x3f) {
+ coarse = 0x1f;
+ }
+ dfllval_conf.bit.COARSE = coarse;
+ // TODO(tannewt): Load this from a well known flash location so that it can be
+ // calibrated during testing.
+ dfllval_conf.bit.FINE = 0x1ff;
+
+ SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 0x1f / 4 ) | // Coarse step is 31, half of the max value
+ SYSCTRL_DFLLMUL_FSTEP( 10 ) |
+ 48000;
+ SYSCTRL->DFLLVAL.reg = dfllval_conf.reg;
+ SYSCTRL->DFLLCTRL.reg = 0;
+ dfll_sync();
+ SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_MODE |
+ SYSCTRL_DFLLCTRL_CCDIS |
+ SYSCTRL_DFLLCTRL_USBCRM | /* USB correction */
+ SYSCTRL_DFLLCTRL_BPLCKC;
+ dfll_sync();
+ SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
+ dfll_sync();
+
+ GCLK_CLKCTRL_Type clkctrl={0};
+ uint16_t temp;
+ GCLK->CLKCTRL.bit.ID = 2; // GCLK_ID - DFLL48M Reference
+ temp = GCLK->CLKCTRL.reg;
+ clkctrl.bit.CLKEN = 1;
+ clkctrl.bit.WRTLOCK = 0;
+ clkctrl.bit.GEN = GCLK_CLKCTRL_GEN_GCLK0_Val;
+ GCLK->CLKCTRL.reg = (clkctrl.reg | temp);
+
+#else
+
+ SYSCTRL->XOSC32K.reg =
+ SYSCTRL_XOSC32K_STARTUP(6) | SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K;
+ SYSCTRL->XOSC32K.bit.ENABLE = 1;
+ while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) == 0)
+ ;
+
+ GCLK->GENDIV.reg = GCLK_GENDIV_ID(1);
+ gclk_sync();
+
+ GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(1) | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_GENEN;
+ gclk_sync();
+
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(0) | GCLK_CLKCTRL_GEN_GCLK1 | GCLK_CLKCTRL_CLKEN;
+ gclk_sync();
+
+ SYSCTRL->DFLLCTRL.bit.ONDEMAND = 0;
+ dfll_sync();
+
+ SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(31) | SYSCTRL_DFLLMUL_FSTEP(511) |
+ SYSCTRL_DFLLMUL_MUL((CPU_FREQUENCY / (32 * 1024)));
+ dfll_sync();
+
+ SYSCTRL->DFLLCTRL.reg |=
+ SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_WAITLOCK | SYSCTRL_DFLLCTRL_QLDIS;
+ dfll_sync();
+
+ SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE;
+
+ while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
+ (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0)
+ ;
+ dfll_sync();
+
+#endif
+
+ // Configure DFLL48M as source for GCLK_GEN 0
+ GCLK->GENDIV.reg = GCLK_GENDIV_ID(0);
+ gclk_sync();
+
+ // Add GCLK_GENCTRL_OE below to output GCLK0 on the SWCLK pin.
+ GCLK->GENCTRL.reg =
+ GCLK_GENCTRL_ID(0) | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_IDC | GCLK_GENCTRL_GENEN;
+ gclk_sync();
+
+ SysTick_Config(1000);
+
+ // Uncomment these two lines to output GCLK0 on the SWCLK pin.
+ // PORT->Group[0].PINCFG[30].bit.PMUXEN = 1;
+ // Set the port mux mask for odd processor pin numbers, PA30 = 30 is even number, PMUXE = PMUX Even
+ // PORT->Group[0].PMUX[30 / 2].reg |= PORT_PMUX_PMUXE_H;
+}
+
+void SysTick_Handler(void) { LED_TICK(); }
diff --git a/bootloader/src/main.c b/bootloader/src/main.c
new file mode 100644
index 0000000..e646dcd
--- /dev/null
+++ b/bootloader/src/main.c
@@ -0,0 +1,325 @@
+/* ----------------------------------------------------------------------------
+ * SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * --------------------
+ * SAM-BA Implementation on SAMD21
+ * --------------------
+ * Requirements to use SAM-BA :
+ *
+ * Supported communication interfaces :
+ * --------------------
+ *
+ * SERCOM5 : RX:PB23 TX:PB22
+ * Baudrate : 115200 8N1
+ *
+ * USB : D-:PA24 D+:PA25
+ *
+ * Pins Usage
+ * --------------------
+ * The following pins are used by the program :
+ * PA25 : input/output
+ * PA24 : input/output
+ * PB23 : input
+ * PB22 : output
+ * PA15 : input
+ *
+ * The application board shall avoid driving the PA25,PA24,PB23,PB22 and PA15
+ * signals
+ * while the boot program is running (after a POR for example)
+ *
+ * Clock system
+ * --------------------
+ * CPU clock source (GCLK_GEN_0) - 8MHz internal oscillator (OSC8M)
+ * SERCOM5 core GCLK source (GCLK_ID_SERCOM5_CORE) - GCLK_GEN_0 (i.e., OSC8M)
+ * GCLK Generator 1 source (GCLK_GEN_1) - 48MHz DFLL in Clock Recovery mode
+ * (DFLL48M)
+ * USB GCLK source (GCLK_ID_USB) - GCLK_GEN_1 (i.e., DFLL in CRM mode)
+ *
+ * Memory Mapping
+ * --------------------
+ * SAM-BA code will be located at 0x0 and executed before any applicative code.
+ *
+ * Applications compiled to be executed along with the bootloader will start at
+ * 0x2000 (samd21) or 0x4000 (samd51)
+ * The bootloader doesn't changes the VTOR register, application code is
+ * taking care of this.
+ *
+ */
+
+#include "uf2.h"
+
+static void check_start_application(void);
+
+static volatile bool main_b_cdc_enable = false;
+extern int8_t led_tick_step;
+
+#ifdef SAMD21
+#define RESET_CONTROLLER PM
+#endif
+#ifdef SAMD51
+#define RESET_CONTROLLER RSTC
+#endif
+
+#if defined(BOOT_KEY_ROW_PIN) && defined(BOOT_KEY_COL_PIN)
+/**
+ * \brief Check whether the boot-hold key (bottom-right Cherry MX button) is
+ * held down. Drives its matrix row low and reads its matrix column back,
+ * the same polarity the app firmware's own matrix scan uses.
+ */
+static bool boot_key_pressed(void) {
+ PORT_PINCFG_Type col_cfg = {0};
+ col_cfg.bit.PMUXEN = false;
+ col_cfg.bit.INEN = true; // external 10k pull-up already on the board
+
+ PORT_PINCFG_Type row_cfg = {0};
+ row_cfg.bit.PMUXEN = false;
+ row_cfg.bit.DRVSTR = true;
+
+ PINCFG(BOOT_KEY_COL_PIN) = col_cfg.reg;
+ PINOP(BOOT_KEY_COL_PIN, DIRCLR); // column stays an input
+
+ PINOP(BOOT_KEY_ROW_PIN, OUTCLR); // pre-set drive level before enabling output
+ PINCFG(BOOT_KEY_ROW_PIN) = row_cfg.reg;
+ PINOP(BOOT_KEY_ROW_PIN, DIRSET); // row -> output, driving low
+
+ for (volatile int i = 0; i < 200; i++) {
+ } // let the row settle through the diode/pull-up RC
+
+ bool pressed = (PINIP(BOOT_KEY_COL_PIN) == 0);
+
+ PINOP(BOOT_KEY_ROW_PIN, DIRCLR); // release row back to high-Z
+ return pressed;
+}
+#endif
+
+/**
+ * \brief Check the application startup condition
+ *
+ */
+static void check_start_application(void) {
+ uint32_t app_start_address;
+
+#if defined(BOOT_KEY_ROW_PIN) && defined(BOOT_KEY_COL_PIN)
+ if (boot_key_pressed()) {
+ /* Stay in bootloader */
+ return;
+ }
+#endif
+
+// Check if there is an IO which will hold us inside the bootloader.
+#if defined(HOLD_PIN) && defined(HOLD_STATE)
+ PORT_PINCFG_Type pincfg = {0};
+ pincfg.bit.PMUXEN = false;
+ pincfg.bit.INEN = true;
+ pincfg.bit.DRVSTR = true;
+
+ PINOP(HOLD_PIN, DIRCLR); // Pin is an input
+
+ #if defined(HOLD_PIN_PULLUP)
+ pincfg.bit.PULLEN = true;
+ PINOP(HOLD_PIN, OUTSET); // Pin is pulled up.
+ #elif defined(HOLD_PIN_PULLDOWN)
+ pincfg.bit.PULLEN = true;
+ PINOP(HOLD_PIN, OUTCLR); // Pin is pulled up.
+ #endif
+ PINCFG(HOLD_PIN) = pincfg.reg;
+
+ if (PINIP(HOLD_PIN) == HOLD_STATE) {
+ /* Stay in bootloader */
+ return;
+ }
+#endif
+
+ /* Load the Reset Handler address of the application */
+ app_start_address = *(uint32_t *)(APP_START_ADDRESS + 4);
+
+ /**
+ * Test reset vector of application @APP_START_ADDRESS+4
+ * Sanity check on the Reset_Handler address
+ */
+ if (app_start_address < APP_START_ADDRESS || app_start_address > FLASH_SIZE) {
+ /* Stay in bootloader */
+ return;
+ }
+
+#if USE_SINGLE_RESET
+ if (SINGLE_RESET()) {
+ if (RESET_CONTROLLER->RCAUSE.bit.POR || *DBL_TAP_PTR != DBL_TAP_MAGIC_QUICK_BOOT) {
+ // the second tap on reset will go into app
+ *DBL_TAP_PTR = DBL_TAP_MAGIC_QUICK_BOOT;
+ // this will be cleared after succesful USB enumeration
+ // this is around 1.5s
+ resetHorizon = timerHigh + 50;
+ return;
+ }
+ }
+#endif
+
+ if (RESET_CONTROLLER->RCAUSE.bit.POR) {
+ *DBL_TAP_PTR = 0;
+ } else if (*DBL_TAP_PTR == DBL_TAP_MAGIC) {
+ *DBL_TAP_PTR = 0;
+ return; // stay in bootloader
+ } else {
+ if (*DBL_TAP_PTR != DBL_TAP_MAGIC_QUICK_BOOT) {
+ *DBL_TAP_PTR = DBL_TAP_MAGIC;
+ delay(500);
+ }
+ *DBL_TAP_PTR = 0;
+ }
+
+ LED_MSC_OFF();
+#if defined(__SAMD21E18A__)
+ RGBLED_set_color(COLOR_LEAVE);
+#endif
+
+ /* Rebase the Stack Pointer */
+ __set_MSP(*(uint32_t *)APP_START_ADDRESS);
+
+ /* Rebase the vector table base address */
+ SCB->VTOR = ((uint32_t)APP_START_ADDRESS & SCB_VTOR_TBLOFF_Msk);
+
+ /* Ensure the MSP/VTOR writes are visible before jumping; without these
+ * barriers the app's first fetch can race the pipeline (observed on
+ * real hardware: identical MSP/VTOR/PC values injected by a halted
+ * debugger boot fine, but the bootloader's own running jump hard-faults
+ * every time). */
+ __DSB();
+ __ISB();
+
+ /* Jump to application Reset Handler in the application */
+ asm("bx %0" ::"r"(app_start_address));
+}
+
+extern char _etext;
+extern char _end;
+
+/**
+ * \brief SAMD21 SAM-BA Main loop.
+ * \return Unused (ANSI-C compatibility).
+ */
+int main(void) {
+ // if VTOR is set, we're not running in bootloader mode; halt
+ if (SCB->VTOR)
+ while (1) {
+ }
+
+#if (USB_VID == 0x239a) && (USB_PID == 0x0013) // Adafruit Metro M0
+ // Delay a bit so SWD programmer can have time to attach.
+ delay(15);
+#endif
+ led_init();
+
+ logmsg("Start");
+ assert((uint32_t)&_etext < APP_START_ADDRESS);
+ // bossac writes at 0x20005000
+ assert(!USE_MONITOR || (uint32_t)&_end < 0x20005000);
+
+ assert(8 << NVMCTRL->PARAM.bit.PSZ == FLASH_PAGE_SIZE);
+ assert(FLASH_PAGE_SIZE * NVMCTRL->PARAM.bit.NVMP == FLASH_SIZE);
+
+ /* Jump in application if condition is satisfied */
+ check_start_application();
+
+ /* We have determined we should stay in the monitor. */
+ /* System initialization */
+ system_init();
+
+ __DMB();
+ __enable_irq();
+
+#if USE_UART
+ /* UART is enabled in all cases */
+ usart_open();
+#endif
+
+ logmsg("Before main loop");
+
+ usb_init();
+
+ // not enumerated yet
+ RGBLED_set_color(COLOR_START);
+ led_tick_step = 10;
+
+ /* Wait for a complete enum on usb or a '#' char on serial line */
+ while (1) {
+ if (USB_Ok()) {
+ if (!main_b_cdc_enable) {
+#if USE_SINGLE_RESET
+ // this might have been set
+ resetHorizon = 0;
+#endif
+ RGBLED_set_color(COLOR_USB);
+ led_tick_step = 1;
+
+#if USE_SCREEN
+ screen_init();
+ draw_drag();
+#endif
+ }
+
+ main_b_cdc_enable = true;
+ }
+
+#if USE_MONITOR
+ // Check if a USB enumeration has succeeded
+ // And com port was opened
+ if (main_b_cdc_enable) {
+ logmsg("entering monitor loop");
+ // SAM-BA on USB loop
+ while (1) {
+ sam_ba_monitor_run();
+ }
+ }
+#if USE_UART
+ /* Check if a '#' has been received */
+ if (!main_b_cdc_enable && usart_sharp_received()) {
+ RGBLED_set_color(COLOR_UART);
+ sam_ba_monitor_init(SAM_BA_INTERFACE_USART);
+ /* SAM-BA on UART loop */
+ while (1) {
+ sam_ba_monitor_run();
+ }
+ }
+#endif
+#else // no monitor
+ if (main_b_cdc_enable) {
+ process_msc();
+ }
+#endif
+
+ if (!main_b_cdc_enable) {
+ // get more predictable timings before the USB is enumerated
+ for (int i = 1; i < 256; ++i) {
+ asm("nop");
+ }
+ }
+ }
+}
diff --git a/bootloader/src/msc.c b/bootloader/src/msc.c
new file mode 100644
index 0000000..02d0414
--- /dev/null
+++ b/bootloader/src/msc.c
@@ -0,0 +1,879 @@
+/**
+ * \file
+ *
+ * \brief USB Device Mass Storage Class (MSC) interface.
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+#define DEFINE_CONFIG_DATA 1
+
+#include "uf2.h"
+
+#include "lib/usb_msc/sbc_protocol.h"
+#include "lib/usb_msc/spc_protocol.h"
+#include "lib/usb_msc/usb_protocol.h"
+#include "lib/usb_msc/usb_protocol_msc.h"
+
+#if !USE_DBG_MSC
+#undef logmsg
+#undef logval
+#define logmsg(...) NOOP
+#define logval(...) NOOP
+#endif
+
+// From sam0/utils/compiler.h in ASF3
+#define le32_to_cpu(x) (x)
+#define cpu_to_le32(x) (x)
+#define CPU_TO_BE32(x) ((uint32_t)__builtin_bswap32((uint32_t)(x)))
+#define cpu_to_be16(x) ((uint16_t)(((uint16_t)(x) >> 8) |\
+ ((uint16_t)(x) << 8)))
+
+#define MSB3(u32) (((uint8_t *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
+#define MSB2(u32) (((uint8_t *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB1(u32) (((uint8_t *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB0(u32) (((uint8_t *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
+
+#define MSB(u16) (((uint8_t *)&(u16))[1]) //!< Most significant byte of \a u16.
+#define LSB(u16) (((uint8_t *)&(u16))[0]) //!< Least significant byte of \a u16.
+
+bool mscReset = false;
+
+void msc_reset(void) {
+ mscReset = true;
+ reset_ep(USB_EP_MSC_IN);
+ reset_ep(USB_EP_MSC_OUT);
+}
+
+//! Structure to receive a CBW packet
+static struct usb_msc_cbw udi_msc_cbw;
+//! Structure to send a CSW packet
+static struct usb_msc_csw udi_msc_csw = {.dCSWSignature = cpu_to_le32(USB_CSW_SIGNATURE)};
+//! Structure with current SCSI sense data
+static struct scsi_request_sense_data udi_msc_sense;
+
+#if USE_MSC_CHECKS
+/**
+ * \brief Stall CBW request
+ */
+static void udi_msc_cbw_invalid(void);
+
+/**
+ * \brief Stall CSW request
+ */
+static void udi_msc_csw_invalid(void);
+#endif
+
+/**
+ * \brief Function to check the CBW length and direction
+ * Call it after SCSI command decode to check integrity of command
+ *
+ * \param alloc_len number of bytes that device want transfer
+ * \param dir_flag Direction of transfer (USB_CBW_DIRECTION_IN/OUT)
+ *
+ * \retval true if the command can be processed
+ */
+static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag);
+//@}
+
+/**
+ * \name Routines to process small data packet
+ */
+//@{
+
+/**
+ * \brief Sends data on MSC IN endpoint
+ * Called by SCSI command which must send a data to host followed by a CSW
+ *
+ * \param buffer Internal RAM buffer to send
+ * \param buf_size Size of buffer to send
+ */
+static void udi_msc_data_send(uint8_t *buffer, uint8_t buf_size);
+
+/**
+ * \name Routines to process CSW packet
+ */
+//@{
+
+/**
+ * \brief Build CSW packet and send it
+ *
+ * Called at the end of SCSI command
+ */
+static void udi_msc_csw_process(void);
+
+/**
+ * \brief Sends CSW
+ *
+ * Called by #udi_msc_csw_process()
+ * or UDD callback when endpoint halt is cleared
+ */
+void udi_msc_csw_send(void);
+
+/**
+ * \name Routines manage sense data
+ */
+//@{
+
+/**
+ * \brief Reinitialize sense data.
+ */
+static void udi_msc_clear_sense(void);
+
+/**
+ * \brief Update sense data with new value to signal a fail
+ *
+ * \param sense_key Sense key
+ * \param add_sense Additional Sense Code
+ * \param lba LBA corresponding at error
+ */
+static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense, uint32_t lba);
+
+/**
+ * \brief Update sense data with new value to signal success
+ */
+static void udi_msc_sense_pass(void);
+
+/**
+ * \brief Update sense data to signal a hardware error on memory
+ */
+static void udi_msc_sense_fail_hardware(void);
+
+#if USE_MSC_CHECKS
+/**
+ * \brief Update sense data to signal that CDB fields are not valid
+ */
+static void udi_msc_sense_fail_cdb_invalid(void);
+#endif
+
+/**
+ * \brief Update sense data to signal that command is not supported
+ */
+static void udi_msc_sense_command_invalid(void);
+//@}
+
+/**
+ * \name Routines manage SCSI Commands
+ */
+//@{
+
+/**
+ * \brief Process SPC Request Sense command
+ * Returns error information about last command
+ */
+static void udi_msc_spc_requestsense(void);
+
+/**
+ * \brief Process SPC Inquiry command
+ * Returns information (name,version) about disk
+ */
+static void udi_msc_spc_inquiry(void);
+
+/**
+ * \brief Checks state of disk
+ *
+ * \retval true if disk is ready, otherwise false and updates sense data
+ */
+static bool udi_msc_spc_testunitready_global(void);
+
+/**
+ * \brief Process test unit ready command
+ * Returns state of logical unit
+ */
+static void udi_msc_spc_testunitready(void);
+
+/**
+ * \brief Process prevent allow medium removal command
+ */
+static void udi_msc_spc_prevent_allow_medium_removal(void);
+
+/**
+ * \brief Process mode sense command
+ *
+ * \param b_sense10 Sense10 SCSI command, if true
+ * \param b_sense10 Sense6 SCSI command, if false
+ */
+static void udi_msc_spc_mode_sense(bool b_sense10);
+
+/**
+ * \brief Process start stop command
+ */
+static void udi_msc_sbc_start_stop(void);
+
+/**
+ * \brief Process read capacity command
+ */
+static void udi_msc_sbc_read_capacity(void);
+
+/**
+ * \brief Process read10 or write10 command
+ *
+ * \param b_read Read transfer, if true,
+ * \param b_read Write transfer, if false
+ */
+static void udi_msc_sbc_trans(bool b_read);
+
+static void udi_msc_read_format_capacity(void);
+
+void udd_ep_set_halt(uint8_t ep) {
+ stall_ep(ep);
+ reset_ep(ep);
+}
+
+#if USE_MSC_CHECKS
+static void udi_msc_cbw_invalid(void) {
+ logmsg("MSC CBW Invalid; halt");
+ udd_ep_set_halt(USB_EP_MSC_OUT);
+
+ // TODO If stall cleared then re-stall it. Only Setup MSC Reset can clear it
+}
+
+static void udi_msc_csw_invalid(void) {
+ logmsg("MSC CSW Invalid; halt");
+ udd_ep_set_halt(USB_EP_MSC_IN);
+
+ // TODO If stall cleared then re-stall it. Only Setup MSC Reset can clear it
+}
+#endif
+
+bool try_read_cbw(struct usb_msc_cbw *cbw, uint8_t ep, PacketBuffer *handoverCache) {
+ if (!USB_ReadCore(NULL, 1, ep, handoverCache))
+ return false; // no data available
+
+ uint32_t nb_received = USB_ReadCore((void *)cbw, sizeof(*cbw), ep, handoverCache);
+
+#if USE_MSC_CHECKS
+ // Check CBW integrity:
+ // transfer status/CBW length/CBW signature
+ if ((sizeof(*cbw) != nb_received) || (cbw->dCBWSignature != cpu_to_le32(USB_CBW_SIGNATURE))) {
+ if (handoverCache)
+ resetIntoBootloader();
+ // (5.2.1) Devices receiving a CBW with an invalid signature should
+ // stall
+ // further traffic on the Bulk In pipe, and either stall further traffic
+ // or accept and discard further traffic on the Bulk Out pipe, until
+ // reset recovery.
+ udi_msc_cbw_invalid();
+ udi_msc_csw_invalid();
+ return false;
+ }
+
+ // in handover mode we don't care about LUN
+ if (handoverCache)
+ return true;
+
+ // Check LUN asked
+ cbw->bCBWLUN &= USB_CBW_LUN_MASK;
+ if (cbw->bCBWLUN > MAX_LUN) {
+ // Bad LUN, then stop command process
+ udi_msc_sense_fail_cdb_invalid();
+ udi_msc_csw_process();
+ return false;
+ }
+#else
+ (void)nb_received;
+#endif
+
+ return true;
+}
+
+void process_msc(void) {
+#if USE_HID || USE_WEBUSB
+ process_hid();
+#endif
+
+ if (!try_read_cbw(&udi_msc_cbw, USB_EP_MSC_OUT, false))
+ return; // no data
+
+ // Prepare CSW residue field with the size requested
+ udi_msc_csw.dCSWDataResidue = le32_to_cpu(udi_msc_cbw.dCBWDataTransferLength);
+
+ // if (SBC_WRITE10 != udi_msc_cbw.CDB[0])
+ // logval("MSC CMD", udi_msc_cbw.CDB[0]);
+
+ // Decode opcode
+ switch (udi_msc_cbw.CDB[0]) {
+ case SPC_REQUEST_SENSE:
+ udi_msc_spc_requestsense();
+ break;
+
+ case SPC_INQUIRY:
+ udi_msc_spc_inquiry();
+ break;
+
+ case SPC_MODE_SENSE6:
+ udi_msc_spc_mode_sense(false);
+ break;
+ case SPC_MODE_SENSE10:
+ udi_msc_spc_mode_sense(true);
+ break;
+
+ case SPC_TEST_UNIT_READY:
+ udi_msc_spc_testunitready();
+ break;
+
+ case SBC_READ_CAPACITY10:
+ udi_msc_sbc_read_capacity();
+ break;
+
+ case SBC_START_STOP_UNIT:
+ udi_msc_sbc_start_stop();
+ break;
+
+ // Accepts request to support plug/plug in case of card reader
+ case SPC_PREVENT_ALLOW_MEDIUM_REMOVAL:
+ udi_msc_spc_prevent_allow_medium_removal();
+ break;
+
+ // Accepts request to support full format from Windows
+ case SBC_VERIFY10:
+ udi_msc_sense_pass();
+ udi_msc_csw_process();
+ break;
+
+ case SBC_READ10:
+ udi_msc_sbc_trans(true);
+ break;
+
+ case SBC_WRITE10:
+ udi_msc_sbc_trans(false);
+ break;
+
+ case 0x23:
+ udi_msc_read_format_capacity();
+ break;
+
+ default:
+ logval("Invalid MSC command", udi_msc_cbw.CDB[0]);
+ udi_msc_sense_command_invalid();
+ udi_msc_csw_process();
+ break;
+ }
+}
+
+static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag) {
+/*
+ * The following cases should result in a phase error:
+ * - Case 2: Hn < Di
+ * - Case 3: Hn < Do
+ * - Case 7: Hi < Di
+ * - Case 8: Hi <> Do
+ * - Case 10: Ho <> Di
+ * - Case 13: Ho < Do
+ */
+#if USE_MSC_CHECKS
+ if (((udi_msc_cbw.bmCBWFlags ^ dir_flag) & USB_CBW_DIRECTION_IN) ||
+ (udi_msc_csw.dCSWDataResidue < alloc_len)) {
+ udi_msc_sense_fail_cdb_invalid();
+ udi_msc_csw_process();
+ return false;
+ }
+#endif
+
+ /*
+ * The following cases should result in a stall and nonzero
+ * residue:
+ * - Case 4: Hi > Dn
+ * - Case 5: Hi > Di
+ * - Case 9: Ho > Dn
+ * - Case 11: Ho > Do
+ */
+ return true;
+}
+
+//---------------------------------------------
+//------- Routines to process small data packet
+
+static void udi_msc_data_send(uint8_t *buffer, uint8_t buf_size) {
+ if (USB_Write((void *)buffer, buf_size, USB_EP_MSC_IN) != buf_size) {
+ // If endpoint not available, then exit process command
+ udi_msc_sense_fail_hardware();
+ udi_msc_csw_process();
+ }
+
+ // Update sense data
+ udi_msc_sense_pass();
+ // Update CSW
+ udi_msc_csw.dCSWDataResidue -= buf_size;
+ udi_msc_csw_process();
+}
+
+//---------------------------------------------
+//------- Routines to process CSW packet
+
+static void udi_msc_csw_process(void) {
+ if (0 != udi_msc_csw.dCSWDataResidue) {
+ logval("left-over residue", udi_msc_csw.dCSWDataResidue);
+
+ /*
+ uint8_t buf[64] = {0};
+ while (udi_msc_csw.dCSWDataResidue > 0) {
+ size_t len = min(udi_msc_csw.dCSWDataResidue, 64);
+ USB_Write((void *)buf, len, USB_EP_MSC_IN);
+ udi_msc_csw.dCSWDataResidue -= len;
+ }
+ */
+
+ /*
+ // Residue not NULL
+ // then STALL next request from USB host on corresponding endpoint
+ if (udi_msc_cbw.bmCBWFlags & USB_CBW_DIRECTION_IN)
+ udd_ep_set_halt(USB_EP_MSC_IN);
+ else
+ udd_ep_set_halt(USB_EP_MSC_OUT);
+ */
+ }
+
+ // Prepare and send CSW
+ udi_msc_csw.dCSWTag = udi_msc_cbw.dCBWTag;
+ udi_msc_csw.dCSWDataResidue = cpu_to_le32(udi_msc_csw.dCSWDataResidue);
+ udi_msc_csw_send();
+}
+
+void udi_msc_csw_send(void) { USB_Write((void *)&udi_msc_csw, sizeof(udi_msc_csw), USB_EP_MSC_IN); }
+
+//---------------------------------------------
+//------- Routines manage sense data
+
+static void udi_msc_clear_sense(void) {
+ memset((uint8_t *)&udi_msc_sense, 0, sizeof(struct scsi_request_sense_data));
+ udi_msc_sense.valid_reponse_code = SCSI_SENSE_VALID | SCSI_SENSE_CURRENT;
+ udi_msc_sense.AddSenseLen = SCSI_SENSE_ADDL_LEN(sizeof(udi_msc_sense));
+}
+
+static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense, uint32_t lba) {
+ logval("MSC sense fail", sense_key);
+ udi_msc_clear_sense();
+ udi_msc_csw.bCSWStatus = USB_CSW_STATUS_FAIL;
+ udi_msc_sense.sense_flag_key = sense_key;
+ udi_msc_sense.information[0] = lba >> 24;
+ udi_msc_sense.information[1] = lba >> 16;
+ udi_msc_sense.information[2] = lba >> 8;
+ udi_msc_sense.information[3] = lba;
+ udi_msc_sense.AddSense = add_sense;
+}
+
+static void udi_msc_sense_pass(void) {
+ udi_msc_clear_sense();
+ udi_msc_csw.bCSWStatus = USB_CSW_STATUS_PASS;
+}
+
+static void udi_msc_sense_fail_hardware(void) {
+ udi_msc_sense_fail(SCSI_SK_HARDWARE_ERROR, SCSI_ASC_NO_ADDITIONAL_SENSE_INFO, 0);
+}
+
+#if USE_MSC_CHECKS
+static void udi_msc_sense_fail_cdb_invalid(void) {
+ udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, SCSI_ASC_INVALID_FIELD_IN_CDB, 0);
+}
+#endif
+
+static void udi_msc_sense_command_invalid(void) {
+ udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, SCSI_ASC_INVALID_COMMAND_OPERATION_CODE, 0);
+}
+
+//---------------------------------------------
+//------- Routines manage SCSI Commands
+
+static void udi_msc_spc_requestsense(void) {
+ uint8_t length = udi_msc_cbw.CDB[4];
+
+ // Can't send more than sense data length
+ if (length > sizeof(udi_msc_sense))
+ length = sizeof(udi_msc_sense);
+
+ if (!udi_msc_cbw_validate(length, USB_CBW_DIRECTION_IN))
+ return;
+ // Send sense data
+ udi_msc_data_send((uint8_t *)&udi_msc_sense, length);
+}
+
+static void udi_msc_read_format_capacity(void) {
+ uint8_t buf[12] = {0,
+ 0,
+ 0,
+ 8, // length
+ (NUM_FAT_BLOCKS >> 24) & 0xFF,
+ (NUM_FAT_BLOCKS >> 16) & 0xFF,
+ (NUM_FAT_BLOCKS >> 8) & 0xFF,
+ (NUM_FAT_BLOCKS >> 0) & 0xFF,
+ 2, // Descriptor Code: Formatted Media
+ 0,
+ (512 >> 8) & 0xff,
+ 0};
+
+ size_t length = 12;
+
+ if (udi_msc_csw.dCSWDataResidue > length)
+ udi_msc_csw.dCSWDataResidue = length;
+
+ if (!udi_msc_cbw_validate(length, USB_CBW_DIRECTION_IN))
+ return;
+ udi_msc_data_send(buf, length);
+}
+
+static void udi_msc_spc_inquiry(void) {
+ uint8_t length;
+ __attribute__((__aligned__(4)))
+ // Constant inquiry data for all LUNs
+ static struct scsi_inquiry_data udi_msc_inquiry_data = {
+ .pq_pdt = SCSI_INQ_PQ_CONNECTED | SCSI_INQ_DT_DIR_ACCESS,
+ .version = 2, // SCSI_INQ_VER_SPC,
+ .flags1 = SCSI_INQ_RMB,
+ .flags3 = SCSI_INQ_RSP_SPC2,
+ .addl_len = 36 - 4, // SCSI_INQ_ADDL_LEN(sizeof(struct scsi_inquiry_data)),
+ // Linux displays this; Windows shows it in Dev Mgr
+ .vendor_id = "",
+ .product_id = "",
+ .product_rev = {'1', '.', '0', '0'},
+ };
+
+ // we use both product_id and vendor_id fields and hope for the best
+ padded_memcpy(udi_msc_inquiry_data.vendor_id, PRODUCT_NAME, 8 + 16);
+
+ length = udi_msc_cbw.CDB[4];
+
+ // Can't send more than inquiry data length
+ if (length > sizeof(udi_msc_inquiry_data))
+ length = sizeof(udi_msc_inquiry_data);
+
+ if (!udi_msc_cbw_validate(length, USB_CBW_DIRECTION_IN))
+ return;
+
+ /*
+if ((0 != (udi_msc_cbw.CDB[1] & (SCSI_INQ_REQ_EVPD | SCSI_INQ_REQ_CMDT))) ||
+ (0 != udi_msc_cbw.CDB[2])) {
+ logval("unsupp", udi_msc_cbw.CDB[1]);
+ // CMDT and EPVD bits are not at 0
+ // PAGE or OPERATION CODE fields are not empty
+ // = No standard inquiry asked
+ udi_msc_sense_fail_cdb_invalid(); // Command is unsupported
+ udi_msc_csw_process();
+ return;
+}
+*/
+
+ // logval("Sense Size", length);
+
+ // Send inquiry data
+ udi_msc_data_send((uint8_t *)&udi_msc_inquiry_data, length);
+}
+
+static bool udi_msc_spc_testunitready_global(void) { return true; }
+
+static void udi_msc_spc_testunitready(void) {
+ if (udi_msc_spc_testunitready_global()) {
+ // LUN ready, then update sense data with status pass
+ udi_msc_sense_pass();
+ }
+ // Send status in CSW packet
+ udi_msc_csw_process();
+}
+
+static void udi_msc_spc_mode_sense(bool b_sense10) {
+ // Union of all mode sense structures
+ union sense_6_10 {
+ struct {
+ struct scsi_mode_param_header6 header;
+ struct spc_control_page_info_execpt sense_data;
+ } s6;
+ struct {
+ struct scsi_mode_param_header10 header;
+ struct spc_control_page_info_execpt sense_data;
+ } s10;
+ };
+
+ uint8_t data_sense_lgt;
+ uint8_t mode;
+ uint8_t request_lgt;
+ struct spc_control_page_info_execpt *ptr_mode;
+ __attribute__((__aligned__(4))) static union sense_6_10 sense;
+
+ // Clear all fields
+ memset(&sense, 0, sizeof(sense));
+
+ // Initialize process
+ if (b_sense10) {
+ request_lgt = udi_msc_cbw.CDB[8];
+ ptr_mode = &sense.s10.sense_data;
+ data_sense_lgt = sizeof(struct scsi_mode_param_header10);
+ } else {
+ request_lgt = udi_msc_cbw.CDB[4];
+ ptr_mode = &sense.s6.sense_data;
+ data_sense_lgt = sizeof(struct scsi_mode_param_header6);
+ }
+
+ // No Block descriptor
+
+ // Fill page(s)
+ mode = udi_msc_cbw.CDB[2] & SCSI_MS_MODE_ALL;
+ if ((SCSI_MS_MODE_INFEXP == mode) || (SCSI_MS_MODE_ALL == mode)) {
+ // Informational exceptions control page (from SPC)
+ ptr_mode->page_code = SCSI_MS_MODE_INFEXP;
+ ptr_mode->page_length = SPC_MP_INFEXP_PAGE_LENGTH;
+ ptr_mode->mrie = SPC_MP_INFEXP_MRIE_NO_SENSE;
+ data_sense_lgt += sizeof(struct spc_control_page_info_execpt);
+ }
+ // Can't send more than mode sense data length
+ if (request_lgt > data_sense_lgt)
+ request_lgt = data_sense_lgt;
+ if (!udi_msc_cbw_validate(request_lgt, USB_CBW_DIRECTION_IN))
+ return;
+
+ // Fill mode parameter header length
+
+ if (b_sense10) {
+ sense.s10.header.mode_data_length = cpu_to_be16((data_sense_lgt - 2));
+ } else {
+ sense.s6.header.mode_data_length = data_sense_lgt - 1;
+ }
+
+ // Send mode sense data
+ udi_msc_data_send((uint8_t *)&sense, request_lgt);
+}
+
+static void udi_msc_spc_prevent_allow_medium_removal(void) {
+#if USE_MSC_CHECKS
+ uint8_t prevent = udi_msc_cbw.CDB[4];
+ if (0 == prevent) {
+ udi_msc_sense_pass();
+ } else {
+ udi_msc_sense_fail_cdb_invalid(); // Command is unsupported
+ }
+#else
+ udi_msc_sense_pass();
+#endif
+ udi_msc_csw_process();
+}
+
+static void udi_msc_sbc_start_stop(void) {
+#if 0
+ bool start = 0x1 & udi_msc_cbw.CDB[4];
+ bool loej = 0x2 & udi_msc_cbw.CDB[4];
+ if (loej) {
+ mem_unload(udi_msc_cbw.bCBWLUN, !start);
+ }
+#endif
+ udi_msc_sense_pass();
+ udi_msc_csw_process();
+}
+
+static void udi_msc_sbc_read_capacity(void) {
+ __attribute__((__aligned__(4))) static struct sbc_read_capacity10_data udi_msc_capacity;
+
+ if (!udi_msc_cbw_validate(sizeof(udi_msc_capacity), USB_CBW_DIRECTION_IN))
+ return;
+
+ udi_msc_capacity.max_lba = NUM_FAT_BLOCKS - 1;
+ // Format capacity data
+ udi_msc_capacity.block_len = CPU_TO_BE32(UDI_MSC_BLOCK_SIZE);
+ udi_msc_capacity.max_lba = CPU_TO_BE32(udi_msc_capacity.max_lba);
+ // Send the corresponding sense data
+ udi_msc_data_send((uint8_t *)&udi_msc_capacity, sizeof(udi_msc_capacity));
+}
+
+__attribute__((__aligned__(4))) static uint8_t block_buffer[UDI_MSC_BLOCK_SIZE];
+static WriteState usbWriteState;
+
+static void udi_msc_sbc_trans(bool b_read) {
+ uint32_t trans_size;
+
+ //! Memory address to execute the command
+ uint32_t udi_msc_addr;
+
+ //! Number of block to transfer
+ uint16_t udi_msc_nb_block;
+
+ // Read/Write command fields (address and number of block)
+ MSB0(udi_msc_addr) = udi_msc_cbw.CDB[2];
+ MSB1(udi_msc_addr) = udi_msc_cbw.CDB[3];
+ MSB2(udi_msc_addr) = udi_msc_cbw.CDB[4];
+ MSB3(udi_msc_addr) = udi_msc_cbw.CDB[5];
+ MSB(udi_msc_nb_block) = udi_msc_cbw.CDB[7];
+ LSB(udi_msc_nb_block) = udi_msc_cbw.CDB[8];
+
+ // Compute number of byte to transfer and valid it
+ trans_size = (uint32_t)udi_msc_nb_block * UDI_MSC_BLOCK_SIZE;
+ if (!udi_msc_cbw_validate(trans_size, (b_read) ? USB_CBW_DIRECTION_IN : USB_CBW_DIRECTION_OUT))
+ return;
+
+#if USE_DBG_MSC
+ logwrite(b_read ? "read @" : "write @");
+ logwritenum(udi_msc_addr);
+ logwrite(" sz:");
+ logwritenum(trans_size);
+ logwrite("\n");
+#endif
+
+ for (uint32_t i = 0; i < udi_msc_nb_block; ++i) {
+ if (!USB_Ok()) {
+ logmsg("Transfer aborted.");
+ return;
+ }
+
+ // logval("readblk", i);
+ if (b_read) {
+ read_block(udi_msc_addr + i, block_buffer);
+ USB_Write(block_buffer, UDI_MSC_BLOCK_SIZE, USB_EP_MSC_IN);
+ } else {
+ USB_ReadBlocking(block_buffer, UDI_MSC_BLOCK_SIZE, USB_EP_MSC_OUT, 0);
+
+#if 0
+ check_uf2_handover(block_buffer, udi_msc_nb_block - i - 1, USB_EP_MSC_IN,
+ USB_EP_MSC_OUT, udi_msc_cbw.dCBWTag);
+#endif
+
+ write_block(udi_msc_addr + i, block_buffer, false, &usbWriteState);
+ led_signal();
+ }
+ udi_msc_csw.dCSWDataResidue -= UDI_MSC_BLOCK_SIZE;
+ }
+
+ udi_msc_sense_pass();
+
+ // Send status of transfer in CSW packet
+ udi_msc_csw_process();
+}
+
+#if USE_MSC_HANDOVER
+static void handover_flash(UF2_HandoverArgs *handover, PacketBuffer *handoverCache,
+ WriteState *state) {
+ for (uint32_t i = 0; i < handover->blocks_remaining; ++i) {
+ USB_ReadBlocking(handover->buffer, UDI_MSC_BLOCK_SIZE, handover->ep_out, handoverCache);
+ write_block(0x1000 + i, handover->buffer, true, state);
+ }
+}
+
+static void process_handover_initial(UF2_HandoverArgs *handover, PacketBuffer *handoverCache,
+ WriteState *state) {
+ struct usb_msc_csw csw = {.dCSWTag = handover->cbw_tag,
+ .dCSWSignature = cpu_to_le32(USB_CSW_SIGNATURE),
+ .bCSWStatus = USB_CSW_STATUS_PASS,
+ .dCSWDataResidue = 0};
+ // write out the block passed from user space
+ write_block(0xfff, handover->buffer, true, state);
+ // read-write remaining blocks
+ handover_flash(handover, handoverCache, state);
+ // send USB response, as the user space isn't gonna do it
+ USB_WriteCore((void *)&csw, sizeof(csw), handover->ep_in, true);
+}
+
+static void process_handover(UF2_HandoverArgs *handover, PacketBuffer *handoverCache,
+ WriteState *state) {
+ struct usb_msc_cbw cbw;
+ int num = 0;
+
+ while (!try_read_cbw(&cbw, handover->ep_out, handoverCache)) {
+ // TODO is this the right value?
+ if (num++ > TIMER_STEP * 50) {
+ resetIntoApp();
+ }
+ }
+
+ struct usb_msc_csw csw = {.dCSWTag = cbw.dCBWTag,
+ .dCSWSignature = cpu_to_le32(USB_CSW_SIGNATURE),
+ .bCSWStatus = USB_CSW_STATUS_PASS,
+ .dCSWDataResidue = le32_to_cpu(cbw.dCBWDataTransferLength)};
+
+ // if (SBC_WRITE10 != udi_msc_cbw.CDB[0])
+ // logval("MSC CMD", udi_msc_cbw.CDB[0]);
+
+ uint16_t udi_msc_nb_block;
+
+ switch (cbw.CDB[0]) {
+ case SPC_TEST_UNIT_READY:
+ // ready, nothing to do
+ break;
+
+ case SBC_WRITE10:
+ MSB(udi_msc_nb_block) = cbw.CDB[7];
+ LSB(udi_msc_nb_block) = cbw.CDB[8];
+ handover->blocks_remaining = udi_msc_nb_block;
+ handover_flash(handover, handoverCache, state);
+ csw.dCSWDataResidue -= UDI_MSC_BLOCK_SIZE * udi_msc_nb_block;
+ break;
+
+ default:
+ resetIntoBootloader();
+ break;
+ }
+
+ USB_WriteCore((void *)&csw, sizeof(csw), handover->ep_in, true);
+}
+
+void handoverPrep() {
+ __disable_irq();
+ __DMB();
+
+ USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK;
+ USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK;
+
+ SCB->VTOR = 0;
+}
+
+static void handover(UF2_HandoverArgs *args) {
+ handoverPrep();
+
+ PacketBuffer cache = {0};
+ WriteState writeState = {0};
+ cache.read_job = 2;
+
+ // They may have 0x80 bit set
+ args->ep_in &= 0xf;
+ args->ep_out &= 0xf;
+
+ process_handover_initial(args, &cache, &writeState);
+ while (1) {
+ process_handover(args, &cache, &writeState);
+ }
+}
+#endif
+
+__attribute__((section(".binfo"))) __attribute__((__used__)) const UF2_BInfo binfo = {
+#ifdef HAS_CONFIG_DATA
+ .config_data = config_data,
+#endif
+#if USE_MSC_HANDOVER
+ .handoverMSC = handover,
+#endif
+#if USE_HID_HANDOVER
+ .handoverHID = hidHandoverLoop,
+#endif
+ .info_uf2 = infoUf2File,
+};
diff --git a/bootloader/src/sam_ba_monitor.c b/bootloader/src/sam_ba_monitor.c
new file mode 100644
index 0000000..2e7b299
--- /dev/null
+++ b/bootloader/src/sam_ba_monitor.c
@@ -0,0 +1,300 @@
+/* ----------------------------------------------------------------------------
+ * SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "uf2.h"
+
+static const char fullVersion[] = "v" SAM_BA_VERSION " [Arduino:XYZ] " __DATE__ " " __TIME__ "\n\r";
+
+/* b_terminal_mode mode (ascii) or hex mode */
+#if USE_CDC_TERMINAL
+volatile bool b_terminal_mode = false;
+#endif
+volatile bool b_sam_ba_interface_usart = false;
+
+void sam_ba_monitor_init(uint8_t com_interface) {
+#if USE_UART
+ // Selects the requested interface for future actions
+ if (com_interface == SAM_BA_INTERFACE_USART) {
+ b_sam_ba_interface_usart = true;
+ }
+#endif
+}
+
+/**
+ * \brief This function allows data rx by USART
+ *
+ * \param *data Data pointer
+ * \param length Length of the data
+ */
+void sam_ba_putdata_term(uint8_t *data, uint32_t length) {
+#if USE_CDC_TERMINAL
+ uint8_t temp, buf[12], *data_ascii;
+ uint32_t i, int_value;
+
+ if (b_terminal_mode) {
+ if (length == 4)
+ int_value = *(uint32_t *)(void *)data;
+ else if (length == 2)
+ int_value = *(uint16_t *)(void *)data;
+ else
+ int_value = *(uint8_t *)(void *)data;
+
+ data_ascii = buf + 2;
+ data_ascii += length * 2 - 1;
+
+ for (i = 0; i < length * 2; i++) {
+ temp = (uint8_t)(int_value & 0xf);
+
+ if (temp <= 0x9)
+ *data_ascii = temp | 0x30;
+ else
+ *data_ascii = temp + 0x37;
+
+ int_value >>= 4;
+ data_ascii--;
+ }
+ buf[0] = '0';
+ buf[1] = 'x';
+ buf[length * 2 + 2] = '\n';
+ buf[length * 2 + 3] = '\r';
+ cdc_write_buf(buf, length * 2 + 4);
+ } else
+#endif
+ cdc_write_buf(data, length);
+ return;
+}
+
+volatile uint32_t sp;
+void call_applet(uint32_t address) {
+ uint32_t app_start_address;
+
+ /* Save current Stack Pointer */
+ sp = __get_MSP();
+
+ /* Rebase the Stack Pointer */
+ __set_MSP(*(uint32_t *)address);
+
+ /* Load the Reset Handler address of the application */
+ app_start_address = *(uint32_t *)(address + 4);
+
+ /* Jump to application Reset Handler in the application */
+ asm("blx %0" ::"r"(app_start_address):"r0","r1","r2","r3","lr");
+
+ /* Rebase the Stack Pointer */
+ __set_MSP(sp);
+}
+
+uint32_t current_number;
+uint32_t i, length;
+uint8_t command, *ptr_data, *ptr, data[SIZEBUFMAX + 1];
+uint8_t j;
+uint32_t u32tmp;
+
+// Prints a 32-bit integer in hex.
+void put_uint32(uint32_t n) {
+ char buff[8];
+ writeNum(buff, n, true);
+ cdc_write_buf(buff, 8);
+}
+
+/**
+ * \brief This function starts the SAM-BA monitor.
+ */
+void sam_ba_monitor_run(void) {
+ ptr_data = NULL;
+ command = 'z';
+
+ // Start waiting some cmd
+ while (1) {
+ process_msc();
+ length = cdc_read_buf(data, SIZEBUFMAX);
+ data[length] = 0;
+ if (length) {
+ logwrite("SERIAL:");
+ logmsg(data);
+ led_signal();
+ }
+ ptr = data;
+ for (i = 0; i < length; i++) {
+ if (*ptr != 0xff) {
+ if (*ptr == '#') {
+#if USE_CDC_TERMINAL
+ if (b_terminal_mode) {
+ cdc_write_buf("\n\r", 2);
+ }
+#endif
+ if (command == 'S') {
+ // Check if some data are remaining in the "data" buffer
+ if (length > i) {
+ // Move current indexes to next avail data
+ // (currently ptr points to "#")
+ ptr++;
+ i++;
+ // We need to add first the remaining data of the
+ // current buffer already read from usb
+ // read a maximum of "current_number" bytes
+ u32tmp = (length - i) < current_number ? (length - i) : current_number;
+ memcpy(ptr_data, ptr, u32tmp);
+ i += u32tmp;
+ ptr += u32tmp;
+ j = u32tmp;
+ }
+ // update i with the data read from the buffer
+ i--;
+ ptr--;
+ // Do we expect more data ?
+ if (j < current_number)
+ cdc_read_buf_xmd(ptr_data, current_number - j);
+
+ __asm("nop");
+ } else if (command == 'R') {
+ cdc_write_buf_xmd(ptr_data, current_number);
+ } else if (command == 'O') {
+ *ptr_data = (char)current_number;
+ } else if (command == 'H') {
+ *((uint16_t *)(void *)ptr_data) = (uint16_t)current_number;
+ } else if (command == 'W') {
+ // detect BOSSA resetting us
+ if ((uint32_t)ptr_data == 0xE000ED0C)
+ RGBLED_set_color(COLOR_LEAVE);
+ *((int *)(void *)ptr_data) = current_number;
+ } else if (command == 'o') {
+ sam_ba_putdata_term(ptr_data, 1);
+ } else if (command == 'h') {
+ current_number = *((uint16_t *)(void *)ptr_data);
+ sam_ba_putdata_term((uint8_t *)¤t_number, 2);
+ } else if (command == 'w') {
+ current_number = *((uint32_t *)(void *)ptr_data);
+ sam_ba_putdata_term((uint8_t *)¤t_number, 4);
+ } else if (command == 'G') {
+ call_applet(current_number);
+ if (b_sam_ba_interface_usart) {
+ cdc_write_buf("\x06", 1);
+ }
+ } else if (command == 'T') {
+#if USE_CDC_TERMINAL
+ b_terminal_mode = 1;
+ cdc_write_buf("\n\r", 2);
+#endif
+ } else if (command == 'N') {
+#if USE_CDC_TERMINAL
+ if (b_terminal_mode == 0) {
+ cdc_write_buf("\n\r", 2);
+ }
+ b_terminal_mode = 0;
+#endif
+ } else if (command == 'V') {
+ cdc_write_buf(fullVersion, sizeof(fullVersion));
+ } else if (command == 'X') {
+ // Syntax: X[ADDR]#
+ // Erase the flash memory starting from ADDR to the end
+ // of flash.
+
+ flash_erase_to_end((uint32_t *) current_number);
+
+ // Notify command completed
+ cdc_write_buf("X\n\r", 3);
+ } else if (command == 'Y') {
+ // This command writes the content of a buffer in SRAM
+ // into flash memory.
+
+ // Syntax: Y[ADDR],0#
+ // Set the starting address of the SRAM buffer.
+
+ // Syntax: Y[ROM_ADDR],[SIZE]#
+ // Write the first SIZE bytes from the SRAM buffer
+ // (previously set) into
+ // flash memory starting from address ROM_ADDR
+
+ static uint32_t *src_buff_addr = NULL;
+
+ if (current_number == 0) {
+ // Set buffer address
+ src_buff_addr = (void *)ptr_data;
+
+ } else {
+ flash_write_words((void *)ptr_data, src_buff_addr, current_number / 4);
+ }
+
+ // Notify command completed
+ cdc_write_buf("Y\n\r", 3);
+ } else if (command == 'Z') {
+ // This command calculate CRC for a given area of
+ // memory.
+ // It's useful to quickly check if a transfer has been
+ // done
+ // successfully.
+
+ // Syntax: Z[START_ADDR],[SIZE]#
+ // Returns: Z[CRC]#
+
+ uint8_t *data = (uint8_t *)ptr_data;
+ uint32_t size = current_number;
+ uint16_t crc = 0;
+ uint32_t i = 0;
+ for (i = 0; i < size; i++)
+ crc = add_crc(*data++, crc);
+
+ // Send response
+ cdc_write_buf("Z", 1);
+ put_uint32(crc);
+ cdc_write_buf("#\n\r", 3);
+ }
+
+ command = 'z';
+ current_number = 0;
+#if USE_CDC_TERMINAL
+ if (b_terminal_mode) {
+ cdc_write_buf(">", 1);
+ }
+#endif
+ } else {
+ if (('0' <= *ptr) && (*ptr <= '9')) {
+ current_number = (current_number << 4) | (*ptr - '0');
+
+ } else if (('A' <= *ptr) && (*ptr <= 'F')) {
+ current_number = (current_number << 4) | (*ptr - 'A' + 0xa);
+
+ } else if (('a' <= *ptr) && (*ptr <= 'f')) {
+ current_number = (current_number << 4) | (*ptr - 'a' + 0xa);
+
+ } else if (*ptr == ',') {
+ ptr_data = (uint8_t *)current_number;
+ current_number = 0;
+
+ } else {
+ command = *ptr;
+ current_number = 0;
+ }
+ }
+ ptr++;
+ }
+ }
+ }
+}
diff --git a/bootloader/src/screen.c b/bootloader/src/screen.c
new file mode 100644
index 0000000..c6da7a6
--- /dev/null
+++ b/bootloader/src/screen.c
@@ -0,0 +1,489 @@
+#include "uf2.h"
+
+#if USE_SCREEN
+
+#include
+
+#define DISPLAY_WIDTH 160
+#define DISPLAY_HEIGHT 128
+
+// Overlap 4x chars by this much.
+#define CHAR4_KERNING 2
+// Width of a single 4x char, adjusted by kerning
+#define CHAR4_KERNED_WIDTH (6 * 4 - CHAR4_KERNING)
+
+#define ST7735_NOP 0x00
+#define ST7735_SWRESET 0x01
+#define ST7735_RDDID 0x04
+#define ST7735_RDDST 0x09
+
+#define ST7735_SLPIN 0x10
+#define ST7735_SLPOUT 0x11
+#define ST7735_PTLON 0x12
+#define ST7735_NORON 0x13
+
+#define ST7735_INVOFF 0x20
+#define ST7735_INVON 0x21
+#define ST7735_DISPOFF 0x28
+#define ST7735_DISPON 0x29
+#define ST7735_CASET 0x2A
+#define ST7735_RASET 0x2B
+#define ST7735_RAMWR 0x2C
+#define ST7735_RAMRD 0x2E
+
+#define ST7735_PTLAR 0x30
+#define ST7735_COLMOD 0x3A
+#define ST7735_MADCTL 0x36
+
+#define ST7735_FRMCTR1 0xB1
+#define ST7735_FRMCTR2 0xB2
+#define ST7735_FRMCTR3 0xB3
+#define ST7735_INVCTR 0xB4
+#define ST7735_DISSET5 0xB6
+
+#define ST7735_PWCTR1 0xC0
+#define ST7735_PWCTR2 0xC1
+#define ST7735_PWCTR3 0xC2
+#define ST7735_PWCTR4 0xC3
+#define ST7735_PWCTR5 0xC4
+#define ST7735_VMCTR1 0xC5
+
+#define ST7735_RDID1 0xDA
+#define ST7735_RDID2 0xDB
+#define ST7735_RDID3 0xDC
+#define ST7735_RDID4 0xDD
+
+#define ST7735_PWCTR6 0xFC
+
+#define ST7735_GMCTRP1 0xE0
+#define ST7735_GMCTRN1 0xE1
+
+uint32_t lookupCfg(uint32_t key, uint32_t defl);
+#define CFG(v) lookupCfg(CFG_##v, 0x42)
+
+uint32_t lookupCfg(uint32_t key, uint32_t defl) {
+ const uint32_t *ptr = UF2_BINFO->config_data;
+ if (!ptr || (((uint32_t)ptr) & 3) || *ptr != CFG_MAGIC0) {
+ // no config data!
+ } else {
+ ptr += 4;
+ while (*ptr) {
+ if (*ptr == key)
+ return ptr[1];
+ ptr += 2;
+ }
+ }
+ if (defl == 0x42)
+ while (1)
+ ;
+ return defl;
+}
+
+void pin_set(int pincfg, int v) {
+ int pin = lookupCfg(pincfg, -1);
+ if (pin < 0)
+ return;
+ if (v) {
+ PINOP(pin, OUTSET);
+ } else {
+ PINOP(pin, OUTCLR);
+ }
+}
+
+void setup_output_pin(int pincfg) {
+ int pin = lookupCfg(pincfg, -1);
+ if (pin < 0)
+ return;
+ PINOP(pin, DIRSET);
+ PINOP(pin, OUTCLR);
+}
+
+#define PINPORT(pin) PORT->Group[(pin) / 32]
+#define pinmask(pin) (1 << (pin & 0x1f))
+
+void transfer(uint8_t *ptr, uint32_t len) {
+ int mosi = CFG(PIN_DISPLAY_MOSI);
+ int sck = CFG(PIN_DISPLAY_SCK);
+
+ volatile uint32_t *mosi_set = &PINPORT(mosi).OUTSET.reg;
+ volatile uint32_t *mosi_clr = &PINPORT(mosi).OUTCLR.reg;
+ volatile uint32_t *sck_tgl = &PINPORT(sck).OUTTGL.reg;
+
+ uint32_t mosi_mask = pinmask(mosi);
+ uint32_t sck_mask = pinmask(sck);
+
+ PINOP(sck, OUTCLR);
+
+ uint8_t mask = 0, b;
+ for (;;) {
+ if (!mask) {
+ if (!len--)
+ break;
+ mask = 0x80;
+ b = *ptr++;
+ }
+ if (b & mask)
+ *mosi_set = mosi_mask;
+ else
+ *mosi_clr = mosi_mask;
+ *sck_tgl = sck_mask;
+ mask >>= 1;
+ *sck_tgl = sck_mask;
+ }
+}
+
+#define DELAY 0x80
+
+// clang-format off
+static const uint8_t initCmds[] = {
+ ST7735_SWRESET, DELAY, // 1: Software reset, 0 args, w/delay
+ 120, // 150 ms delay
+ ST7735_SLPOUT , DELAY, // 2: Out of sleep mode, 0 args, w/delay
+ 120, // 500 ms delay
+ ST7735_INVOFF , 0 , // 13: Don't invert display, no args, no delay
+ ST7735_COLMOD , 1 , // 15: set color mode, 1 arg, no delay:
+ 0x05, // 16-bit color
+ ST7735_GMCTRP1, 16 , // 1: Magical unicorn dust, 16 args, no delay:
+ 0x02, 0x1c, 0x07, 0x12,
+ 0x37, 0x32, 0x29, 0x2d,
+ 0x29, 0x25, 0x2B, 0x39,
+ 0x00, 0x01, 0x03, 0x10,
+ ST7735_NORON , DELAY, // 3: Normal display on, no args, w/delay
+ 10, // 10 ms delay
+ ST7735_DISPON , DELAY, // 4: Main screen turn on, no args w/delay
+ 10,
+ 0, 0 // END
+};
+// clang-format on
+
+static uint8_t cmdBuf[20];
+
+#define SET_DC(v) pin_set(CFG_PIN_DISPLAY_DC, v)
+#define SET_CS(v) pin_set(CFG_PIN_DISPLAY_CS, v)
+
+static void scr_delay(unsigned msec) {
+ int k = msec * 15000;
+ while (k--)
+ asm("nop");
+}
+
+static void sendCmd(uint8_t *buf, int len) {
+ // make sure cmd isn't on stack
+ if (buf != cmdBuf)
+ memcpy(cmdBuf, buf, len);
+ buf = cmdBuf;
+
+ SET_DC(0);
+ SET_CS(0);
+
+ transfer(buf, 1);
+
+ SET_DC(1);
+
+ len--;
+ buf++;
+ if (len > 0)
+ transfer(buf, len);
+
+ SET_CS(1);
+}
+
+static void sendCmdSeq(const uint8_t *buf) {
+ while (*buf) {
+ cmdBuf[0] = *buf++;
+ int v = *buf++;
+ int len = v & ~DELAY;
+ // note that we have to copy to RAM
+ memcpy(cmdBuf + 1, buf, len);
+ sendCmd(cmdBuf, len + 1);
+ buf += len;
+ if (v & DELAY) {
+ scr_delay(*buf++);
+ }
+ }
+}
+
+static uint32_t palXOR;
+
+static void setAddrWindow(int x, int y, int w, int h) {
+ w += x - 1;
+ h += y - 1;
+ uint8_t cmd0[] = {ST7735_RASET, 0, (uint8_t)x, (uint8_t)(w >> 8), (uint8_t)w};
+ uint8_t cmd1[] = {ST7735_CASET, 0, (uint8_t)y, (uint8_t)(h >> 8), (uint8_t)h};
+ sendCmd(cmd1, sizeof(cmd1));
+ sendCmd(cmd0, sizeof(cmd0));
+}
+
+static void configure(uint8_t madctl, uint32_t frmctr1) {
+ uint8_t cmd0[] = {ST7735_MADCTL, madctl};
+ uint8_t cmd1[] = {ST7735_FRMCTR1, (uint8_t)(frmctr1 >> 16), (uint8_t)(frmctr1 >> 8),
+ (uint8_t)frmctr1};
+ sendCmd(cmd0, sizeof(cmd0));
+ sendCmd(cmd1, cmd1[3] == 0xff ? 3 : 4);
+}
+
+#define COL0(r, g, b) ((((r) >> 3) << 11) | (((g) >> 2) << 5) | ((b) >> 3))
+#define COL(c) COL0((c >> 16) & 0xff, (c >> 8) & 0xff, c & 0xff)
+
+const uint16_t palette[] = {
+ COL(0x000000), // 0
+ COL(0xffffff), // 1
+ COL(0xff2121), // 2
+ COL(0xff93c4), // 3
+ COL(0xff8135), // 4
+ COL(0xfff609), // 5
+ COL(0x249ca3), // 6
+ COL(0x78dc52), // 7
+ COL(0x003fad), // 8
+ COL(0x87f2ff), // 9
+ COL(0x8e2ec4), // 10
+ COL(0xa4839f), // 11
+ COL(0x5c406c), // 12
+ COL(0xe5cdc4), // 13
+ COL(0x91463d), // 14
+ COL(0x000000), // 15
+};
+
+uint8_t fb[168 * 128];
+extern const uint8_t font8[];
+extern const uint8_t fileLogo[];
+extern const uint8_t pendriveLogo[];
+extern const uint8_t arrowLogo[];
+
+static void printch(int x, int y, int col, const uint8_t *fnt) {
+ for (int i = 0; i < 6; ++i) {
+ uint8_t *p = fb + (x + i) * DISPLAY_HEIGHT + y;
+ uint8_t mask = 0x01;
+ for (int j = 0; j < 8; ++j) {
+ if (*fnt & mask)
+ *p = col;
+ p++;
+ mask <<= 1;
+ }
+ fnt++;
+ }
+}
+
+static void printch4(int x, int y, int col, const uint8_t *fnt) {
+ for (int i = 0; i < 6 * 4; ++i) {
+ uint8_t *p = fb + (x + i) * DISPLAY_HEIGHT + y;
+ uint8_t mask = 0x01;
+ for (int j = 0; j < 8; ++j) {
+ for (int k = 0; k < 4; ++k) {
+ if (*fnt & mask)
+ *p = col;
+ p++;
+ }
+ mask <<= 1;
+ }
+ if ((i & 3) == 3)
+ fnt++;
+ }
+}
+
+void printicon(int x, int y, int col, const uint8_t *icon) {
+ int w = *icon++;
+ int h = *icon++;
+ int sz = *icon++;
+
+ uint8_t mask = 0x80;
+ int runlen = 0;
+ int runbit = 0;
+ uint8_t lastb = 0x00;
+
+ for (int i = 0; i < w; ++i) {
+ uint8_t *p = fb + (x + i) * DISPLAY_HEIGHT + y;
+ for (int j = 0; j < h; ++j) {
+ int c = 0;
+ if (mask != 0x80) {
+ if (lastb & mask)
+ c = 1;
+ mask <<= 1;
+ } else if (runlen) {
+ if (runbit)
+ c = 1;
+ runlen--;
+ } else {
+ if (sz-- <= 0)
+ panic(10);
+ lastb = *icon++;
+ if (lastb & 0x80) {
+ runlen = lastb & 63;
+ runbit = lastb & 0x40;
+ } else {
+ mask = 0x01;
+ }
+ --j;
+ continue; // restart
+ }
+ if (c)
+ *p = col;
+ p++;
+ }
+ }
+}
+
+void print(int x, int y, int col, const char *text) {
+ int x0 = x;
+ while (*text) {
+ char c = *text++;
+ if (c == '\r')
+ continue;
+ if (c == '\n') {
+ x = x0;
+ y += 10;
+ continue;
+ }
+ /*
+ if (x + 8 > DISPLAY_WIDTH) {
+ x = x0;
+ y += 10;
+ }
+ */
+ if (c < ' ')
+ c = '?';
+ if (c >= 0x7f)
+ c = '?';
+ c -= ' ';
+ printch(x, y, col, &font8[c * 6]);
+ x += 6;
+ }
+}
+
+void print4(int x, int y, int col, const char *text) {
+ while (*text) {
+ char c = *text++;
+ c -= ' ';
+ printch4(x, y, col, &font8[c * 6]);
+ x += CHAR4_KERNED_WIDTH;
+ if (x + CHAR4_KERNED_WIDTH > DISPLAY_WIDTH) {
+ // Next char won't fit.
+ return;
+ }
+ }
+}
+
+void draw_screen() {
+ if (lookupCfg(CFG_PIN_DISPLAY_SCK, 1000) == 1000)
+ return;
+
+ cmdBuf[0] = ST7735_RAMWR;
+ sendCmd(cmdBuf, 1);
+
+ SET_DC(1);
+ SET_CS(0);
+
+ uint8_t *p = fb;
+
+ if (lookupCfg(CFG_DISPLAY_TYPE, 7735) == 7735) {
+ for (int i = 0; i < DISPLAY_WIDTH; ++i) {
+ for (int j = 0; j < DISPLAY_HEIGHT; ++j) {
+ uint16_t color = palette[*p++ & 0xf];
+ uint8_t cc[] = {color >> 8, color & 0xff};
+ transfer(cc, 2);
+ }
+ }
+ } else {
+ // ILI9341/st7789(320*240*p8b) DISPLAY
+ for (int i = 0; i < DISPLAY_WIDTH; ++i) {
+ for (int j = 0; j < DISPLAY_HEIGHT - 8; j++) {
+ uint16_t color = palette[*(p + j) & 0xf];
+ uint8_t cc[] = {color >> 8, color & 0xff};
+ transfer(cc, 2);
+ transfer(cc, 2);
+ }
+ for (int j = 0; j < DISPLAY_HEIGHT - 8; j++) {
+ uint16_t color = palette[*(p + j) & 0xf];
+ uint8_t cc[] = {color >> 8, color & 0xff};
+ transfer(cc, 2);
+ transfer(cc, 2);
+ }
+ p += DISPLAY_HEIGHT;
+ }
+ }
+
+ SET_CS(1);
+}
+
+void drawBar(int y, int h, int c) {
+ for (int x = 0; x < DISPLAY_WIDTH; ++x) {
+ memset(fb + x * DISPLAY_HEIGHT + y, c, h);
+ }
+}
+
+void draw_hf2() {
+ print4(20, 22, 5, "<-->");
+ print(40, 110, 7, "flashing...");
+ draw_screen();
+}
+
+void draw_drag() {
+ drawBar(0, 52, 7);
+ drawBar(52, 55, 8);
+ drawBar(107, 14, 4);
+
+ // Center PRODUCT_NAME and UF2_VERSION_BASE.
+ int name_x = (DISPLAY_WIDTH - (6 * 4 - CHAR4_KERNING) * (int) strlen(PRODUCT_NAME)) / 2;
+ print4(name_x >= 0 ? name_x : 0, 5, 1, PRODUCT_NAME);
+ int version_x = (DISPLAY_WIDTH - 6 * (int) strlen(UF2_VERSION_BASE)) / 2;
+ print(version_x >= 0 ? version_x : 0, 40, 6, UF2_VERSION_BASE);
+ print(23, 110, 1, "arcade.makecode.com");
+
+#define DRAG 70
+#define DRAGX 10
+ printicon(DRAGX + 20, DRAG + 5, 1, fileLogo);
+ printicon(DRAGX + 66, DRAG, 1, arrowLogo);
+ printicon(DRAGX + 108, DRAG, 1, pendriveLogo);
+ print(10, DRAG - 12, 1, "arcade.uf2");
+ print(90, DRAG - 12, 1, VOLUME_LABEL);
+
+ draw_screen();
+}
+
+void screen_early_init() {
+ setup_output_pin(CFG_PIN_DISPLAY_BL);
+}
+
+void screen_init() {
+ if (lookupCfg(CFG_PIN_DISPLAY_SCK, 1000) == 1000)
+ return;
+
+ setup_output_pin(CFG_PIN_DISPLAY_SCK);
+ setup_output_pin(CFG_PIN_DISPLAY_MOSI);
+ setup_output_pin(CFG_PIN_DISPLAY_BL);
+ setup_output_pin(CFG_PIN_DISPLAY_DC);
+ setup_output_pin(CFG_PIN_DISPLAY_RST);
+ setup_output_pin(CFG_PIN_DISPLAY_CS);
+
+ SET_CS(1);
+ SET_DC(1);
+
+ pin_set(CFG_PIN_DISPLAY_BL, 1);
+
+ pin_set(CFG_PIN_DISPLAY_RST, 0);
+ scr_delay(20);
+ pin_set(CFG_PIN_DISPLAY_RST, 1);
+ scr_delay(20);
+
+ sendCmdSeq(initCmds);
+
+ uint32_t cfg0 = CFG(DISPLAY_CFG0);
+ //uint32_t cfg2 = CFG(DISPLAY_CFG2);
+ uint32_t frmctr1 = CFG(DISPLAY_CFG1);
+ palXOR = (cfg0 & 0x1000000) ? 0xffffff : 0x000000;
+ uint32_t madctl = cfg0 & 0xff;
+ uint32_t offX = (cfg0 >> 8) & 0xff;
+ uint32_t offY = (cfg0 >> 16) & 0xff;
+ //uint32_t freq = (cfg2 & 0xff);
+
+ //offX = (CFG(DISPLAY_WIDTH) - DISPLAY_WIDTH) / 2; //commented out, breaks ILI9341 compatibility
+ //offY = (CFG(DISPLAY_HEIGHT) - DISPLAY_HEIGHT) / 2;
+
+ // DMESG("configure screen: FRMCTR1=%p MADCTL=%p SPI at %dMHz", frmctr1, madctl, freq);
+ configure(madctl, frmctr1);
+ setAddrWindow(offX, offY, CFG(DISPLAY_WIDTH), CFG(DISPLAY_HEIGHT));
+
+ memset(fb, 0, sizeof(fb));
+}
+
+#endif
diff --git a/bootloader/src/startup_samd21.c b/bootloader/src/startup_samd21.c
new file mode 100644
index 0000000..7195853
--- /dev/null
+++ b/bootloader/src/startup_samd21.c
@@ -0,0 +1,289 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD21
+ *
+ * Copyright (c) 2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "board_config.h"
+#include "samd21.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+//void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_USB
+void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SERCOM4
+void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC6
+void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_ADC
+void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC
+void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_DAC
+void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PTC
+void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_I2S
+void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC1
+void AC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+ /* Configure Initial Stack Pointer, using linker-generated symbols */
+ .pvStack = (void*) (&_estack),
+
+ .pfnReset_Handler = (void*) Reset_Handler,
+ .pfnNMI_Handler = (void*) NMI_Handler,
+ .pfnHardFault_Handler = (void*) HardFault_Handler,
+ .pvReservedM12 = (void*) (0UL), /* Reserved */
+ .pvReservedM11 = (void*) (0UL), /* Reserved */
+ .pvReservedM10 = (void*) (0UL), /* Reserved */
+ .pvReservedM9 = (void*) (0UL), /* Reserved */
+ .pvReservedM8 = (void*) (0UL), /* Reserved */
+ .pvReservedM7 = (void*) (0UL), /* Reserved */
+ .pvReservedM6 = (void*) (0UL), /* Reserved */
+ .pfnSVC_Handler = (void*) SVC_Handler,
+ .pvReservedM4 = (void*) (0UL), /* Reserved */
+ .pvReservedM3 = (void*) (0UL), /* Reserved */
+ .pfnPendSV_Handler = (void*) PendSV_Handler,
+ .pfnSysTick_Handler = (void*) SysTick_Handler,
+
+ /* Configurable interrupts */
+ .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
+ .pfnSYSCTRL_Handler = (void*) SYSCTRL_Handler, /* 1 System Control */
+ .pfnWDT_Handler = (void*) WDT_Handler, /* 2 Watchdog Timer */
+ .pfnRTC_Handler = (void*) RTC_Handler, /* 3 Real-Time Counter */
+ .pfnEIC_Handler = (void*) EIC_Handler, /* 4 External Interrupt Controller */
+ .pfnNVMCTRL_Handler = (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
+ .pfnDMAC_Handler = (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
+#ifdef ID_USB
+ .pfnUSB_Handler = (void*) USB_Handler, /* 7 Universal Serial Bus */
+#else
+ .pvReserved7 = (void*) (0UL), /* 7 Reserved */
+#endif
+ .pfnEVSYS_Handler = (void*) EVSYS_Handler, /* 8 Event System Interface */
+ .pfnSERCOM0_Handler = (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
+ .pfnSERCOM1_Handler = (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
+ .pfnSERCOM2_Handler = (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
+ .pfnSERCOM3_Handler = (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+ .pfnSERCOM4_Handler = (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
+#else
+ .pvReserved13 = (void*) (0UL), /* 13 Reserved */
+#endif
+#ifdef ID_SERCOM5
+ .pfnSERCOM5_Handler = (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
+#else
+ .pvReserved14 = (void*) (0UL), /* 14 Reserved */
+#endif
+ .pfnTCC0_Handler = (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
+ .pfnTCC1_Handler = (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
+ .pfnTCC2_Handler = (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
+ .pfnTC3_Handler = (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
+ .pfnTC4_Handler = (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
+ .pfnTC5_Handler = (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
+#ifdef ID_TC6
+ .pfnTC6_Handler = (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
+#else
+ .pvReserved21 = (void*) (0UL), /* 21 Reserved */
+#endif
+#ifdef ID_TC7
+ .pfnTC7_Handler = (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
+#else
+ .pvReserved22 = (void*) (0UL), /* 22 Reserved */
+#endif
+#ifdef ID_ADC
+ .pfnADC_Handler = (void*) ADC_Handler, /* 23 Analog Digital Converter */
+#else
+ .pvReserved23 = (void*) (0UL), /* 23 Reserved */
+#endif
+#ifdef ID_AC
+ .pfnAC_Handler = (void*) AC_Handler, /* 24 Analog Comparators 0 */
+#else
+ .pvReserved24 = (void*) (0UL), /* 24 Reserved */
+#endif
+#ifdef ID_DAC
+ .pfnDAC_Handler = (void*) DAC_Handler, /* 25 Digital Analog Converter */
+#else
+ .pvReserved25 = (void*) (0UL), /* 25 Reserved */
+#endif
+#ifdef ID_PTC
+ .pfnPTC_Handler = (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
+#else
+ .pvReserved26 = (void*) (0UL), /* 26 Reserved */
+#endif
+#ifdef ID_I2S
+ .pfnI2S_Handler = (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
+#else
+ .pvReserved27 = (void*) (0UL), /* 27 Reserved */
+#endif
+#ifdef ID_AC1
+ .pfnAC1_Handler = (void*) AC1_Handler /* 28 Analog Comparators 1 */
+#else
+ .pvReserved28 = (void*) (0UL) /* 28 Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+
+ /* Initialize the relocate segment */
+ pSrc = &_etext;
+ pDest = &_srelocate;
+
+ if (pSrc != pDest) {
+ for (; pDest < &_erelocate;) {
+ *pDest++ = *pSrc++;
+ }
+ }
+
+ /* Clear the zero segment */
+ for (pDest = &_szero; pDest < &_ezero;) {
+ *pDest++ = 0;
+ }
+
+ /* Set the vector table base address */
+ pSrc = (uint32_t *) & _sfixed;
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+ /* Change default QOS values to have the best performance and correct USB behaviour */
+ SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+#if defined(ID_USB)
+ USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+ USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+#endif
+ DMAC->QOSCTRL.bit.DQOS = 2;
+ DMAC->QOSCTRL.bit.FQOS = 2;
+ DMAC->QOSCTRL.bit.WRBQOS = 2;
+
+ /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+ NVMCTRL->CTRLB.bit.MANW = 1;
+
+ /* Initialize the C library */
+ //__libc_init_array();
+
+ /* Branch to main function */
+ main();
+
+ /* Infinite loop */
+ while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+ while (1) {
+ }
+}
+
+void HardFault_Handler(void)
+{
+ while (1) {
+ }
+}
diff --git a/bootloader/src/uart_driver.c b/bootloader/src/uart_driver.c
new file mode 100644
index 0000000..f04dd58
--- /dev/null
+++ b/bootloader/src/uart_driver.c
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------------
+ * SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "board_config.h"
+#include "uart_driver.h"
+
+bool uart_drv_error_flag = false;
+
+uint32_t uart_get_sercom_index(Sercom *sercom_instance) {
+ /* Save all available SERCOM instances for compare. */
+ Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+
+ /* Find index for sercom instance. */
+ for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+ if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
+ return i;
+ }
+ }
+
+ return 0;
+}
+
+void uart_basic_init(Sercom *sercom, uint16_t baud_val, enum uart_pad_settings pad_conf) {
+ /* Wait for synchronization */
+ while (sercom->USART.SYNCBUSY.bit.ENABLE)
+ ;
+ /* Disable the SERCOM UART module */
+ sercom->USART.CTRLA.bit.ENABLE = 0;
+ /* Wait for synchronization */
+ while (sercom->USART.SYNCBUSY.bit.SWRST)
+ ;
+ /* Perform a software reset */
+ sercom->USART.CTRLA.bit.SWRST = 1;
+ /* Wait for synchronization */
+ while (sercom->USART.CTRLA.bit.SWRST)
+ ;
+ /* Wait for synchronization */
+ while (sercom->USART.SYNCBUSY.bit.SWRST || sercom->USART.SYNCBUSY.bit.ENABLE)
+ ;
+ /* Update the UART pad settings, mode and data order settings */
+ sercom->USART.CTRLA.reg = pad_conf | SERCOM_USART_CTRLA_MODE(1) | SERCOM_USART_CTRLA_DORD;
+ /* Wait for synchronization */
+ while (sercom->USART.SYNCBUSY.bit.CTRLB)
+ ;
+ /* Enable transmit and receive and set data size to 8 bits */
+ sercom->USART.CTRLB.reg =
+ SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_CHSIZE(0);
+ /* Load the baud value */
+ sercom->USART.BAUD.reg = baud_val;
+ /* Wait for synchronization */
+ while (sercom->USART.SYNCBUSY.bit.ENABLE)
+ ;
+ /* Enable SERCOM UART */
+ sercom->USART.CTRLA.bit.ENABLE = 1;
+}
+
+void uart_disable(Sercom *sercom) {
+ /* Wait for synchronization */
+ while (sercom->USART.SYNCBUSY.bit.ENABLE)
+ ;
+ /* Disable SERCOM UART */
+ sercom->USART.CTRLA.bit.ENABLE = 0;
+}
+
+void uart_write_byte(Sercom *sercom, uint8_t data) {
+ /* Wait for Data Register Empty flag */
+ while (!sercom->USART.INTFLAG.bit.DRE)
+ ;
+ /* Write the data to DATA register */
+ sercom->USART.DATA.reg = (uint16_t)data;
+}
+
+uint8_t uart_read_byte(Sercom *sercom) {
+ /* Wait for Receive Complete flag */
+ while (!sercom->USART.INTFLAG.bit.RXC)
+ ;
+ /* Check for errors */
+ if (sercom->USART.STATUS.bit.PERR || sercom->USART.STATUS.bit.FERR ||
+ sercom->USART.STATUS.bit.BUFOVF)
+ /* Set the error flag */
+ uart_drv_error_flag = true;
+ /* Return the read data */
+ return ((uint8_t)sercom->USART.DATA.reg);
+}
+
+void uart_write_buffer_polled(Sercom *sercom, uint8_t *ptr, uint16_t length) {
+ /* Do the following for specified length */
+ do {
+ /* Wait for Data Register Empty flag */
+ while (!sercom->USART.INTFLAG.bit.DRE)
+ ;
+ /* Send data from the buffer */
+ sercom->USART.DATA.reg = (uint16_t)*ptr++;
+ } while (length--);
+}
+
+void uart_read_buffer_polled(Sercom *sercom, uint8_t *ptr, uint16_t length) {
+ /* Do the following for specified length */
+ do {
+ /* Wait for Receive Complete flag */
+ while (!sercom->USART.INTFLAG.bit.RXC)
+ ;
+ /* Check for errors */
+ if (sercom->USART.STATUS.bit.PERR || sercom->USART.STATUS.bit.FERR ||
+ sercom->USART.STATUS.bit.BUFOVF)
+ /* Set the error flag */
+ uart_drv_error_flag = true;
+ /* Store the read data to the buffer */
+ *ptr++ = (uint8_t)sercom->USART.DATA.reg;
+ } while (length--);
+}
\ No newline at end of file
diff --git a/bootloader/src/usart_sam_ba.c b/bootloader/src/usart_sam_ba.c
new file mode 100644
index 0000000..c62e94e
--- /dev/null
+++ b/bootloader/src/usart_sam_ba.c
@@ -0,0 +1,495 @@
+/* ----------------------------------------------------------------------------
+ * SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2014, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "uf2.h"
+#include "uart_driver.h"
+
+/* Variable to let the main task select the appropriate communication interface
+ */
+volatile uint8_t b_sharp_received;
+
+/* RX and TX Buffers + rw pointers for each buffer */
+volatile uint8_t buffer_rx_usart[USART_BUFFER_SIZE];
+
+volatile uint8_t idx_rx_read;
+volatile uint8_t idx_rx_write;
+
+volatile uint8_t buffer_tx_usart[USART_BUFFER_SIZE];
+
+volatile uint8_t idx_tx_read;
+volatile uint8_t idx_tx_write;
+
+/* Test for timeout in AT91F_GetChar */
+uint8_t error_timeout;
+uint16_t size_of_data;
+uint8_t mode_of_transfer;
+
+#define BOOT_USART_PAD(n) BOOT_USART_PAD##n
+
+/**
+ * \brief Open the given USART
+ */
+void usart_open() {
+ uint32_t port;
+ uint8_t pin;
+
+ /* Configure the port pins for SERCOM_USART */
+ if (BOOT_USART_PAD0 != PINMUX_UNUSED) {
+ /* Mask 6th bit in pin number to check whether it is greater than 32
+ * i.e., PORTB pin */
+ port = (BOOT_USART_PAD0 & 0x200000) >> 21;
+ pin = BOOT_USART_PAD0 >> 16;
+ PORT->Group[port].PINCFG[(pin - (port * 32))].bit.PMUXEN = 1;
+ PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg &= ~(0xF << (4 * (pin & 0x01u)));
+ PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg |= (BOOT_USART_PAD0 & 0xFF)
+ << (4 * (pin & 0x01u));
+ }
+ if (BOOT_USART_PAD1 != PINMUX_UNUSED) {
+ /* Mask 6th bit in pin number to check whether it is greater than 32
+ * i.e., PORTB pin */
+ port = (BOOT_USART_PAD1 & 0x200000) >> 21;
+ pin = BOOT_USART_PAD1 >> 16;
+ PORT->Group[port].PINCFG[(pin - (port * 32))].bit.PMUXEN = 1;
+ PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg &= ~(0xF << (4 * (pin & 0x01u)));
+ PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg |= (BOOT_USART_PAD1 & 0xFF)
+ << (4 * (pin & 0x01u));
+ }
+ if (BOOT_USART_PAD2 != PINMUX_UNUSED) {
+ /* Mask 6th bit in pin number to check whether it is greater than 32
+ * i.e., PORTB pin */
+ port = (BOOT_USART_PAD2 & 0x200000) >> 21;
+ pin = BOOT_USART_PAD2 >> 16;
+ PORT->Group[port].PINCFG[(pin - (port * 32))].bit.PMUXEN = 1;
+ PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg &= ~(0xF << (4 * (pin & 0x01u)));
+ PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg |= (BOOT_USART_PAD2 & 0xFF)
+ << (4 * (pin & 0x01u));
+ }
+ if (BOOT_USART_PAD3 != PINMUX_UNUSED) {
+ /* Mask 6th bit in pin number to check whether it is greater than 32
+ * i.e., PORTB pin */
+ port = (BOOT_USART_PAD3 & 0x200000) >> 21;
+ pin = BOOT_USART_PAD3 >> 16;
+ PORT->Group[port].PINCFG[(pin - (port * 32))].bit.PMUXEN = 1;
+ PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg &= ~(0xF << (4 * (pin & 0x01u)));
+ PORT->Group[port].PMUX[(pin - (port * 32)) / 2].reg |= (BOOT_USART_PAD3 & 0xFF)
+ << (4 * (pin & 0x01u));
+ }
+
+ #ifdef SAMD21
+ uint32_t inst = uart_get_sercom_index(BOOT_USART_MODULE);
+ /* Enable clock for BOOT_USART_MODULE */
+ PM->APBCMASK.reg |= (1u << (inst + PM_APBCMASK_SERCOM0_Pos));
+
+ /* Set GCLK_GEN0 as source for GCLK_ID_SERCOMx_CORE */
+ GCLK_CLKCTRL_Type clkctrl = {0};
+ uint16_t temp;
+ GCLK->CLKCTRL.bit.ID = inst + GCLK_ID_SERCOM0_CORE;
+ temp = GCLK->CLKCTRL.reg;
+ clkctrl.bit.CLKEN = true;
+ clkctrl.bit.WRTLOCK = false;
+ clkctrl.bit.GEN = GCLK_CLKCTRL_GEN_GCLK0_Val;
+ GCLK->CLKCTRL.reg = (clkctrl.reg | temp);
+ #endif
+
+ #ifdef SAMD51
+ GCLK->PCHCTRL[BOOT_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+ GCLK->PCHCTRL[BOOT_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+ MCLK->BOOT_USART_MASK.reg |= BOOT_USART_BUS_CLOCK_INDEX ;
+ #endif
+
+ /* Baud rate 115200 - clock 8MHz -> BAUD value-50436 */
+ uart_basic_init(BOOT_USART_MODULE, 50436, BOOT_USART_PAD_SETTINGS);
+
+ // Initialize flag
+ b_sharp_received = false;
+ idx_rx_read = 0;
+ idx_rx_write = 0;
+ idx_tx_read = 0;
+ idx_tx_write = 0;
+
+ error_timeout = 0;
+}
+
+/**
+ * \brief Configures communication line
+ *
+ */
+void usart_close(void) { uart_disable(BOOT_USART_MODULE); }
+
+/**
+ * \brief Puts a byte on usart line
+ * The type int is used to support printf redirection from compiler LIB.
+ *
+ * \param value Value to put
+ *
+ * \return \c 1 if function was successfully done, otherwise \c 0.
+ */
+int usart_putc(int value) {
+ uart_write_byte(BOOT_USART_MODULE, (uint8_t)value);
+ return 1;
+}
+
+int usart_getc(void) {
+ uint16_t retval;
+ // Wait until input buffer is filled
+ while (!(usart_is_rx_ready()))
+ ;
+ retval = (uint16_t)uart_read_byte(BOOT_USART_MODULE);
+ // usart_read_wait(&usart_sam_ba, &retval);
+ return (int)retval;
+}
+
+int usart_sharp_received(void) {
+ if (usart_is_rx_ready()) {
+ if (usart_getc() == SHARP_CHARACTER)
+ return (true);
+ }
+ return (false);
+}
+
+bool usart_is_rx_ready(void) {
+ return (BOOT_USART_MODULE->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC);
+}
+
+int usart_readc(void) {
+ int retval;
+ retval = buffer_rx_usart[idx_rx_read];
+ idx_rx_read = (idx_rx_read + 1) & (USART_BUFFER_SIZE - 1);
+ return (retval);
+}
+
+// Send given data (polling)
+uint32_t usart_putdata(void const *data, uint32_t length) {
+ uint32_t i;
+ uint8_t *ptrdata;
+ ptrdata = (uint8_t *)data;
+ for (i = 0; i < length; i++) {
+ usart_putc(*ptrdata);
+ ptrdata++;
+ }
+ return (i);
+}
+
+// Get data from comm. device
+uint32_t usart_getdata(void *data, uint32_t length) {
+ uint8_t *ptrdata;
+ ptrdata = (uint8_t *)data;
+ *ptrdata = usart_getc();
+ return (1);
+}
+
+static uint16_t crcCache[256];
+
+//*----------------------------------------------------------------------------
+//* \fn add_crc
+//* \brief Compute the CRC
+//*----------------------------------------------------------------------------
+uint16_t add_crc(uint8_t ch, unsigned short crc0) {
+ if (!crcCache[1]) {
+ for (int ptr = 0; ptr < 256; ptr++) {
+ uint16_t crc = (int)ptr << 8;
+ for (uint16_t cmpt = 0; cmpt < 8; cmpt++) {
+ if (crc & 0x8000)
+ crc = crc << 1 ^ CRC16POLY;
+ else
+ crc = crc << 1;
+ }
+ crcCache[ptr] = crc;
+ }
+ }
+
+ return ((crc0 << 8) ^ crcCache[((crc0 >> 8) ^ ch) & 0xff]) & 0xffff;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn getbytes
+//* \brief
+//*----------------------------------------------------------------------------
+static uint16_t getbytes(uint8_t *ptr_data, uint16_t length) {
+ uint16_t crc = 0;
+ uint16_t cpt;
+ uint8_t c;
+
+ for (cpt = 0; cpt < length; ++cpt) {
+ c = usart_getc();
+ if (error_timeout)
+ return 1;
+ crc = add_crc(c, crc);
+ // crc = (crc << 8) ^ xcrc16tab[(crc>>8) ^ c];
+ if (size_of_data || mode_of_transfer) {
+ *ptr_data++ = c;
+ if (length == PKTLEN_128)
+ size_of_data--;
+ }
+ }
+
+ return crc;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn putPacket
+//* \brief Used by Xup to send packets.
+//*----------------------------------------------------------------------------
+static int putPacket(uint8_t *tmppkt, uint8_t sno) {
+ uint32_t i;
+ uint16_t chksm;
+ uint8_t data;
+
+ chksm = 0;
+
+ usart_putc(SOH);
+
+ usart_putc(sno);
+ usart_putc((uint8_t) ~(sno));
+
+ for (i = 0; i < PKTLEN_128; i++) {
+ if (size_of_data || mode_of_transfer) {
+ data = *tmppkt++;
+ size_of_data--;
+ } else
+ data = 0x00;
+
+ usart_putc(data);
+
+ // chksm = (chksm<<8) ^ xcrc16tab[(chksm>>8)^data];
+ chksm = add_crc(data, chksm);
+ }
+
+ /* An "endian independent way to extract the CRC bytes. */
+ usart_putc((uint8_t)(chksm >> 8));
+ usart_putc((uint8_t)chksm);
+
+ return (usart_getc()); /* Wait for ack */
+}
+
+//*----------------------------------------------------------------------------
+//* \fn getPacket
+//* \brief Used by Xdown to retrieve packets.
+//*----------------------------------------------------------------------------
+uint8_t getPacket(uint8_t *ptr_data, uint8_t sno) {
+ uint8_t seq[2];
+ uint16_t crc, xcrc;
+
+ getbytes(seq, 2);
+ xcrc = getbytes(ptr_data, PKTLEN_128);
+ if (error_timeout)
+ return (false);
+
+ /* An "endian independent way to combine the CRC bytes. */
+ crc = (uint16_t)usart_getc() << 8;
+ crc += (uint16_t)usart_getc();
+
+ if (error_timeout == 1)
+ return (false);
+
+ if ((crc != xcrc) || (seq[0] != sno) || (seq[1] != (uint8_t)(~sno))) {
+ usart_putc(CAN);
+ return (false);
+ }
+
+ usart_putc(ACK);
+ return (true);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn Xup
+//* \brief Called when a transfer from target to host is being made (considered
+//* an upload).
+//*----------------------------------------------------------------------------
+// static void Xup(char *ptr_data, uint16_t length)
+// Send given data (polling) using xmodem (if necessary)
+uint32_t usart_putdata_xmd(void const *data, uint32_t length) {
+ uint8_t c, sno = 1;
+ uint8_t done;
+ uint8_t *ptr_data = (uint8_t *)data;
+ error_timeout = 0;
+ if (!length)
+ mode_of_transfer = 1;
+ else {
+ size_of_data = length;
+ mode_of_transfer = 0;
+ }
+
+ if (length & (PKTLEN_128 - 1)) {
+ length += PKTLEN_128;
+ length &= ~(PKTLEN_128 - 1);
+ }
+
+ /* Startup synchronization... */
+ /* Wait to receive a NAK or 'C' from receiver. */
+ done = 0;
+ while (!done) {
+ c = (uint8_t)usart_getc();
+ if (error_timeout) { // Test for timeout in usart_getc
+ error_timeout = 0;
+ c = (uint8_t)usart_getc();
+ if (error_timeout) {
+ error_timeout = 0;
+ return (0);
+ }
+ }
+ switch (c) {
+ case NAK:
+ done = 1;
+ // ("CSM");
+ break;
+ case 'C':
+ done = 1;
+ // ("CRC");
+ break;
+ case 'q': /* ELS addition, not part of XMODEM spec. */
+ return (0);
+ default:
+ break;
+ }
+ }
+
+ done = 0;
+ sno = 1;
+ while (!done) {
+ c = (uint8_t)putPacket((uint8_t *)ptr_data, sno);
+ if (error_timeout) { // Test for timeout in usart_getc
+ error_timeout = 0;
+ return (0);
+ }
+ switch (c) {
+ case ACK:
+ ++sno;
+ length -= PKTLEN_128;
+ ptr_data += PKTLEN_128;
+ // ("A");
+ break;
+ case NAK:
+ // ("N");
+ break;
+ case CAN:
+ case EOT:
+ default:
+ done = 0;
+ break;
+ }
+ if (!length) {
+ usart_putc(EOT);
+ usart_getc(); /* Flush the ACK */
+ break;
+ }
+ // ("!");
+ }
+
+ mode_of_transfer = 0;
+ // ("Xup_done.");
+ return (1);
+ // return(0);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn Xdown
+//* \brief Called when a transfer from host to target is being made (considered
+//* an download).
+//*----------------------------------------------------------------------------
+// static void Xdown(char *ptr_data, uint16_t length)
+// Get data from comm. device using xmodem (if necessary)
+uint32_t usart_getdata_xmd(void *data, uint32_t length) {
+ uint32_t timeout;
+ char c;
+ uint8_t *ptr_data = (uint8_t *)data;
+ uint32_t b_run, nbr_of_timeout = 100;
+ uint8_t sno = 0x01;
+ uint32_t data_transfered = 0;
+
+ // Copied from legacy source code ... might need some tweaking
+ uint32_t loops_per_second =
+ CPU_FREQUENCY / 10; /* system_clock_source_get_hz(BOOT_USART_GCLK_GEN_SOURCE) / 10; */
+
+ error_timeout = 0;
+
+ if (length == 0)
+ mode_of_transfer = 1;
+ else {
+ size_of_data = length;
+ mode_of_transfer = 0;
+ }
+
+ /* Startup synchronization... */
+ /* Continuously send NAK or 'C' until sender responds. */
+ // ("Xdown");
+ while (1) {
+ usart_putc('C');
+ timeout = loops_per_second;
+ while (!(usart_is_rx_ready()) && timeout)
+ timeout--;
+ if (timeout)
+ break;
+
+ if (!(--nbr_of_timeout))
+ return (0);
+ // return -1;
+ }
+
+ b_run = true;
+ // ("Got response");
+ while (b_run != false) {
+ c = (char)usart_getc();
+ if (error_timeout) { // Test for timeout in usart_getc
+ error_timeout = 0;
+ return (0);
+ // return (-1);
+ }
+ switch (c) {
+ case SOH: /* 128-byte incoming packet */
+ // ("O");
+ b_run = getPacket(ptr_data, sno);
+ if (error_timeout) { // Test for timeout in usart_getc
+ error_timeout = 0;
+ return (0);
+ // return (-1);
+ }
+ if (b_run == true) {
+ ++sno;
+ ptr_data += PKTLEN_128;
+ data_transfered += PKTLEN_128;
+ }
+ break;
+ case EOT: // ("E");
+ usart_putc(ACK);
+ b_run = false;
+ break;
+ case CAN: // ("C");
+ case ESC: /* "X" User-invoked abort */
+ default:
+ b_run = false;
+ break;
+ }
+ // ("!");
+ }
+ mode_of_transfer = 0;
+ return (true);
+ // return(b_run);
+}
diff --git a/bootloader/src/utils.c b/bootloader/src/utils.c
new file mode 100644
index 0000000..9cc05a0
--- /dev/null
+++ b/bootloader/src/utils.c
@@ -0,0 +1,218 @@
+#include "uf2.h"
+#include "neopixel.h"
+
+static uint32_t timerLow;
+uint32_t timerHigh, resetHorizon;
+
+void delay(uint32_t ms) {
+// SAMD21 starts up at 1mhz by default.
+#ifdef SAMD21
+ ms <<= 8;
+#endif
+// SAMD51 starts up at 48mhz by default.
+#ifdef SAMD51
+ ms <<= 12;
+#endif
+ for (int i = 1; i < ms; ++i) {
+ asm("nop");
+ }
+}
+
+void timerTick(void) {
+ if (timerLow-- == 0) {
+ timerLow = TIMER_STEP;
+ timerHigh++;
+ if (resetHorizon && timerHigh >= resetHorizon) {
+ resetHorizon = 0;
+ resetIntoApp();
+ }
+ }
+}
+
+void panic(int code) {
+ logval("PANIC", code);
+ while (1) {
+ }
+}
+
+int writeNum(char *buf, uint32_t n, bool full) {
+ int i = 0;
+ int sh = 28;
+ while (sh >= 0) {
+ int d = (n >> sh) & 0xf;
+ if (full || d || sh == 0 || i) {
+ buf[i++] = d > 9 ? 'A' + d - 10 : '0' + d;
+ }
+ sh -= 4;
+ }
+ return i;
+}
+
+void resetIntoApp() {
+ // reset without waiting for double tap (only works for one reset)
+ RGBLED_set_color(COLOR_LEAVE);
+ *DBL_TAP_PTR = DBL_TAP_MAGIC_QUICK_BOOT;
+ NVIC_SystemReset();
+}
+
+void resetIntoBootloader() {
+ // reset without waiting for double tap (only works for one reset)
+ *DBL_TAP_PTR = DBL_TAP_MAGIC;
+ NVIC_SystemReset();
+}
+
+#if USE_LOGS
+struct LogStore logStoreUF2;
+
+void logreset() {
+ logStoreUF2.ptr = 0;
+ logmsg("Reset logs.");
+}
+
+void logwritenum(uint32_t n) {
+ char buff[9];
+ buff[writeNum(buff, n, false)] = 0;
+ logwrite("0x");
+ logwrite(buff);
+}
+
+void logwrite(const char *msg) {
+ const int jump = sizeof(logStoreUF2.buffer) / 4;
+ if (logStoreUF2.ptr >= sizeof(logStoreUF2.buffer) - jump) {
+ logStoreUF2.ptr -= jump;
+ memmove(logStoreUF2.buffer, logStoreUF2.buffer + jump, logStoreUF2.ptr);
+ }
+ int l = strlen(msg);
+ if (l + logStoreUF2.ptr >= sizeof(logStoreUF2.buffer)) {
+ logwrite("TOO LONG!\n");
+ return;
+ }
+ memcpy(logStoreUF2.buffer + logStoreUF2.ptr, msg, l);
+ logStoreUF2.ptr += l;
+ logStoreUF2.buffer[logStoreUF2.ptr] = 0;
+}
+
+void logmsg(const char *msg) {
+ logwrite(msg);
+ logwrite("\n");
+}
+
+void logval(const char *lbl, uint32_t v) {
+ logwrite(lbl);
+ logwrite(": ");
+ logwritenum(v);
+ logwrite("\n");
+}
+#endif
+
+static uint32_t now;
+static uint32_t signal_end;
+int8_t led_tick_step = 1;
+static uint8_t limit = 200;
+
+void led_tick() {
+ now++;
+ if (signal_end) {
+ if (now == signal_end - 1000) {
+ LED_MSC_ON();
+ }
+ if (now == signal_end) {
+ signal_end = 0;
+ }
+ } else {
+ uint8_t curr = now & 0xff;
+ if (curr == 0) {
+ LED_MSC_ON();
+ if (limit < 10 || limit > 250) {
+ led_tick_step = -led_tick_step;
+ }
+ limit += led_tick_step;
+ } else if (curr == limit) {
+ LED_MSC_OFF();
+ }
+ }
+}
+
+void led_signal() {
+ if (signal_end < now) {
+ signal_end = now + 2000;
+ LED_MSC_OFF();
+ }
+}
+
+void led_init() {
+#if defined(LED_PIN)
+ PINOP(LED_PIN, DIRSET);
+#endif
+ LED_MSC_ON();
+
+#if defined(BOARD_RGBLED_CLOCK_PIN)
+ // using APA102, set pins to outputs
+ PINOP(BOARD_RGBLED_CLOCK_PIN, DIRSET);
+ PINOP(BOARD_RGBLED_DATA_PIN, DIRSET);
+
+ // This won't work for neopixel, because we're running at 1MHz or thereabouts...
+ RGBLED_set_color(COLOR_LEAVE);
+#endif
+
+#if USE_SCREEN
+ // turn display backlight
+ screen_early_init();
+#endif
+}
+
+#if defined(BOARD_RGBLED_CLOCK_PIN)
+void write_apa_byte(uint8_t x) {
+ for (uint8_t i = 0x80; i != 0; i >>= 1) {
+ if (x & i)
+ PINOP(BOARD_RGBLED_DATA_PIN, OUTSET);
+ else
+ PINOP(BOARD_RGBLED_DATA_PIN, OUTCLR);
+
+ PINOP(BOARD_RGBLED_CLOCK_PIN, OUTSET);
+ // for (uint8_t j=0; j<25; j++) /* 0.1ms */
+ // __asm__ __volatile__("");
+
+ PINOP(BOARD_RGBLED_CLOCK_PIN, OUTCLR);
+ // for (uint8_t j=0; j<25; j++) /* 0.1ms */
+ // __asm__ __volatile__("");
+ }
+}
+#endif
+
+void RGBLED_set_color(uint32_t color) {
+#if defined(BOARD_RGBLED_CLOCK_PIN)
+ write_apa_byte(0x0);
+ write_apa_byte(0x0);
+ write_apa_byte(0x0);
+ write_apa_byte(0x0);
+
+ write_apa_byte(0xFF);
+ write_apa_byte(color >> 16);
+ write_apa_byte(color >> 8);
+ write_apa_byte(color);
+
+ write_apa_byte(0xFF);
+ write_apa_byte(0xFF);
+ write_apa_byte(0xFF);
+ write_apa_byte(0xFF);
+
+ // set clock port low for ~10ms
+ delay(50);
+#elif defined(BOARD_NEOPIXEL_PIN)
+ uint8_t buf[BOARD_NEOPIXEL_COUNT * 3];
+#if 0
+ memset(buf, 0, sizeof(buf));
+ buf[0] = color >> 8;
+ buf[1] = color >> 16;
+ buf[2] = color;
+#else
+ for (int i = 0; i < BOARD_NEOPIXEL_COUNT * 3; i += 3) {
+ buf[i + 0] = color >> 8;
+ buf[i + 1] = color >> 16;
+ buf[i + 2] = color;
+ }
+#endif
+ neopixel_send_buffer(buf, BOARD_NEOPIXEL_COUNT * 3);
+#endif
+}
diff --git a/doc/08_development.md b/doc/08_development.md
index 9e50f00..f9607ee 100644
--- a/doc/08_development.md
+++ b/doc/08_development.md
@@ -26,9 +26,9 @@ pio run -e versapad --target upload
Der Upload nutzt `upload_openocd.py`, das das von PlatformIO installierte
OpenOCD mit `interface/cmsis-dap.cfg` und `target/at91samdXX.cfg` startet.
-Das in `platformio.ini` nur als Beispiel enthaltene Environment
-`versapad_usb` ist auskommentiert und mit dem aktuellen NVM-/Linker-Layout
-nicht als unterstützt anzusehen.
+Für App-Updates über USB (nach einem einmaligen Bootloader-Flash) gibt es
+zusätzlich `env:versapad_usb`, siehe
+[10_usb_bootloader.md](10_usb_bootloader.md).
## Was beim Start passiert
@@ -63,6 +63,7 @@ und NVM-Schreibvorgängen. Es gibt keinen Scheduler und keine Threads.
| LEDs | `05_led_system.md` | `CButton.*`, `hal/ws2812.*` |
| Persistente Config | `06_nvm_config.md` | `config/nvm_config.*`, Linker-Skripte |
| Host-Protokoll | `07_serial_protocol.md` | `hal/usb_serial.*`, Controller |
+| USB-Bootloader | `10_usb_bootloader.md` | `bootloader/`, `variants/versapad/linker_scripts/gcc/flash_with_bootloader.ld`, `boards/versapad.json`, `uf2conv.py`, `upload_uf2.py` |
## Verifikation
diff --git a/doc/09_known_limitations.md b/doc/09_known_limitations.md
index be5152d..9c79ffa 100644
--- a/doc/09_known_limitations.md
+++ b/doc/09_known_limitations.md
@@ -3,19 +3,33 @@
Diese Liste beschreibt den aktuellen Implementierungsstand nach den
Robustheitskorrekturen. Sie ist keine Liste bereits umgesetzter Features.
-## Bootloader-Ziel bleibt nicht unterstützt
+## USB-Bootloader hat einen eingeschränkten Gültigkeitsbereich
-Das aktive Ziel `versapad_nobl` reserviert den kompletten Bereich
-`0x1FB00..0x1FFFF` für Makros und Config. Das auskommentierte
-USB-Bootloader-Environment verwendet dagegen weiterhin eine historische
-Board-/Linker-Konfiguration und ist nicht als Produktionsziel verifiziert.
+Der UF2-Bootloader (`bootloader/`, App-Environment `env:versapad_usb`,
+Details in [10_usb_bootloader.md](10_usb_bootloader.md)) ist auf echter
+Hardware verifiziert und ergänzt den SWD-Weg, ersetzt ihn aber nicht: der
+Bootloader selbst muss weiterhin einmalig per Atmel-ICE/SWD geflasht werden.
-Die aktive Boarddatei benennt die MCU als `samd21g17d`, setzt für den
+Verbleibende Einschränkungen:
+
+- `uf2conv.py`/`upload_uf2.py` (Repo-Root) suchen das `VERSABOOT`-Laufwerk
+ nur über die Windows-API, keine macOS/Linux-Unterstützung.
+- Die Bootloader-USB-PID (`0x0043`) ist kollisionsfrei verifiziert, aber kein
+ offiziell registrierter Wert unter Adafruits VID `0x239A`.
+- Kein Software-Trigger, um aus der laufenden App heraus in den
+ Bootloader-Modus zu wechseln — nur der physische Weg (Kabel ziehen, Taste
+ halten, wieder einstecken).
+- Bootloader-Flash-Auslastung ~90 % (7364 von 8192 Byte), wenig Puffer für
+ Änderungen am Bootloader selbst.
+
+Sowohl `boards/versapad_nobl.json` (SWD-Ziel) als auch `boards/versapad.json`
+(USB-Bootloader-Ziel) benennen die MCU als `samd21g17d`, setzen für den
Arduino-Core aber weiterhin das Kompatibilitätsmakro `__SAMD21G18A__`. Der
PlatformIO-Build meldet korrekt 128 KiB physischen Flash, 16 KiB RAM und
-129.792 Byte nutzbaren Firmwarebereich. Vor device-spezifischen
-Core-Änderungen sollte die historische Makro-Abweichung trotzdem geprüft
-werden.
+129.792 Byte (`versapad_nobl`) beziehungsweise 121.600 Byte
+(`versapad`, abzüglich 8 KiB Bootloader) nutzbaren Firmwarebereich. Vor
+device-spezifischen Core-Änderungen sollte die historische Makro-Abweichung
+trotzdem geprüft werden.
## Event-Queue hat eine feste Kapazität
diff --git a/doc/10_usb_bootloader.md b/doc/10_usb_bootloader.md
new file mode 100644
index 0000000..0397fa9
--- /dev/null
+++ b/doc/10_usb_bootloader.md
@@ -0,0 +1,104 @@
+# USB-Bootloader (UF2)
+
+Zweiter Firmware-Update-Weg neben SWD: ein UF2-Bootloader unter
+`bootloader/` erlaubt, die App-Firmware über USB zu aktualisieren, ohne
+Atmel-ICE. Der Bootloader selbst wird einmalig per SWD geflasht; danach
+reicht für App-Updates ein PlatformIO-Befehl.
+
+## Speicherlayout
+
+| Bereich | Adresse | Größe | Environment |
+|---|---|---|---|
+| Bootloader | `0x00000..0x01FFF` | 8 KiB | `versapad_bootloader` (in `bootloader/`) |
+| App-Firmware | `0x02000..0x1FAFF` | 118,75 KiB | `versapad_usb` |
+| NVM (Makros + Config) | `0x1FB00..0x1FFFF` | 1,25 KiB | — |
+
+Gleiches NVM-Layout wie beim SWD-Ziel `versapad_nobl`
+(siehe [06_nvm_config.md](06_nvm_config.md)); nur die Firmware-Obergrenze
+sinkt um die 8 KiB Bootloader. Linkerskript:
+`variants/versapad/linker_scripts/gcc/flash_with_bootloader.ld`, Boarddatei:
+`boards/versapad.json`.
+
+## Bootloader-Einstieg ohne Reset-Taster
+
+Die Platine hat keinen dedizierten Reset-/Boot-Taster. Statt eines
+physischen Pins wird die unterste rechte Cherry-MX-Taste (`key_id 24`,
+COL4 × ROW4, siehe [01_matrix.md](01_matrix.md)) beim Boot geprüft:
+`check_start_application()` in `bootloader/src/main.c` treibt ROW4 kurz auf
+LOW und liest COL4 zurück — noch vor der App-Adress-Validierung, funktioniert
+also auch bei kaputter oder fehlender App-Firmware.
+
+Bedienung: USB-Kabel ziehen, Taste gedrückt halten, wieder einstecken (Taste
+weiter halten) → Board bootet in den Massenspeicher-Modus (`VERSABOOT`).
+Ohne gehaltene Taste startet die App normal.
+
+## Bauen und Flashen
+
+Bootloader einmalig per SWD (überschreibt nur `0x0000..0x1FFF`):
+
+```bash
+cd bootloader
+pio run -e versapad_bootloader --target upload
+```
+
+Danach App-Firmware per USB (Board vorher wie oben in den Bootloader-Modus
+versetzen):
+
+```bash
+pio run -e versapad_usb --target upload
+```
+
+Baut die App, wandelt `firmware.bin` über `uf2conv.py` (Repo-Root, eigene
+minimale Implementierung, kein Upstream-Code) in `firmware.uf2` und kopiert
+es über `upload_uf2.py` aufs erkannte `VERSABOOT`-Laufwerk. Der Bootloader
+erkennt den Schreibzugriff und springt selbständig in die neue App.
+
+`upload_uf2.py` sucht das Laufwerk aktuell nur über die Windows-API
+(`GetVolumeInformationW`) — keine macOS/Linux-Unterstützung.
+
+## Herkunft und Details
+
+Der Bootloader ist abgeleitet und stark eingekürzt aus
+[microsoft/uf2-samdx1](https://github.com/microsoft/uf2-samdx1) (MIT), auf
+den `SAMD21G17D`-Chip dieses Boards zugeschnitten. Herkunft, Lizenz und
+vollständige Implementierungsdetails stehen in `bootloader/README.md`.
+
+## Hardwaretest (2026-08-05) und gefundene Bugs
+
+Kompletter Weg auf echter Hardware verifiziert: Bootloader-Flash,
+USB-Enumeration, Tastencheck-Einstieg, App-Firmware per `.uf2` schreiben,
+automatischer Rücksprung in die neue App. Details, Fehlerbilder und Fixes
+stehen in `bootloader/README.md` unter "Hardwaretest"; kurz zusammengefasst:
+
+- **Fehlende Synchronisationsbarriere beim Sprung Bootloader→App.** Der
+ Sprung (`__set_MSP` → `SCB->VTOR` → `bx`) faultete bei jedem
+ eigenständigen Boot. Fix: `__DSB(); __ISB();` vor dem `bx` in
+ `check_start_application()` — von ARM für dieses Pattern vorgeschrieben,
+ fehlte im vendorten Code.
+- **USB-PID-Kollision.** Die ursprünglich übernommene PID `0x0011` ist
+ Adafruits eigene Gemma-M0-Bootloader-PID; Windows-Rechner mit
+ installiertem Adafruit-Treiber banden das Board fälschlich als
+ `Adafruit Circuit Playground`-COM-Port statt als Massenspeicher. Fix:
+ eigene PID `0x0043`.
+- **OpenOCD-Falle beim manuellen SWD-Debuggen:** `program datei.elf verify`
+ ohne explizite Zieladresse hat wiederholt den Bootloader mit rohen
+ ELF-Datei-Bytes überschrieben, sobald Bootloader- und App-Flash im selben
+ OpenOCD-Aufruf kombiniert wurden. Bei manuellem Flashen beider Bereiche
+ immer `.bin` mit expliziter Adresse und getrennte OpenOCD-Aufrufe
+ verwenden — Details in `bootloader/README.md`, "Achtung bei manuellem
+ SWD-Flashen".
+
+## Bekannte Einschränkungen
+
+- Bootloader-Flash-Auslastung ~90 % (7364 von 8192 Byte) — wenig Puffer für
+ Änderungen am Bootloader selbst.
+- Kein Status-LED-Feedback im Bootloader-Modus (nur WS2812-Kette, dafür ist
+ der Original-Code nicht ausgelegt).
+- USB-PID `0x0043` ist kollisionsfrei verifiziert, aber kein offiziell
+ registrierter Wert unter Adafruits VID `0x239A`.
+- `upload_uf2.py` ist Windows-only (siehe oben).
+- Kein Software-Trigger, um aus der laufenden App heraus in den Bootloader
+ zurückzuspringen — nur der physische Kabel-raus/Taste-halten/Kabel-rein-Weg.
+ Wäre über einen neuen CDC-Befehl (siehe
+ [07_serial_protocol.md](07_serial_protocol.md)) nachrüstbar, der dieselbe
+ `DBL_TAP_MAGIC`-RAM-Adresse setzt und `NVIC_SystemReset()` aufruft.
diff --git a/doc/INDEX.md b/doc/INDEX.md
index 91852c7..d70d4d3 100644
--- a/doc/INDEX.md
+++ b/doc/INDEX.md
@@ -17,6 +17,7 @@ Bereiche stehen ausdrücklich in
| [07_serial_protocol.md](07_serial_protocol.md) | 8-Byte-Protokoll, Config-/Makro-Transfer, ACK/NACK |
| [08_development.md](08_development.md) | Setup, Build, Einstieg nach Änderungstyp, Verifikation |
| [09_known_limitations.md](09_known_limitations.md) | Aktuelle technische Einschränkungen und Risiken |
+| [10_usb_bootloader.md](10_usb_bootloader.md) | UF2-Bootloader, Speicherlayout, Tastencheck-Einstieg, USB-Flashweg |
Die Repository-weiten Richtlinien und der kompakte LLM-Kontext stehen in
[`../AGENTS.md`](../AGENTS.md).
@@ -29,3 +30,4 @@ Die Repository-weiten Richtlinien und der kompakte LLM-Kontext stehen in
- Action-Semantik und HID-Hold: [03_action_engine.md](03_action_engine.md)
- CDC-Protokoll und Chunk-Zahlen: [07_serial_protocol.md](07_serial_protocol.md)
- bekannte Risiken vor strukturellen Änderungen: [09_known_limitations.md](09_known_limitations.md)
+- Firmware per USB statt SWD flashen: [10_usb_bootloader.md](10_usb_bootloader.md)
diff --git a/platformio.ini b/platformio.ini
index 5375d4a..a2b71a8 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -22,8 +22,11 @@ upload_protocol = custom
extra_scripts = upload_openocd.py
debug_tool = openocd
-; ── USB SAM-BA (nur wenn Bootloader geflasht ist) ─────────────────────────────
-; [env:versapad_usb]
-; extends = common
-; board = versapad
-; upload_protocol = sam-ba
+; ── USB UF2 (nur wenn bootloader/ geflasht ist) ────────────────────────────────
+; Der eigene Bootloader spricht UF2/Massenspeicher, kein SAM-BA. upload_uf2.py
+; erzeugt aus firmware.bin ein .uf2 und kopiert es aufs VERSABOOT-Laufwerk.
+[env:versapad_usb]
+extends = common
+board = versapad
+upload_protocol = custom
+extra_scripts = upload_uf2.py
diff --git a/uf2conv.py b/uf2conv.py
new file mode 100644
index 0000000..0053f09
--- /dev/null
+++ b/uf2conv.py
@@ -0,0 +1,83 @@
+#!/usr/bin/env python3
+"""Minimal .bin -> .uf2 converter for the VersaMCU UF2 bootloader.
+
+Standalone reimplementation of the block format microsoft/uf2-samdx1's
+uf2conv.py produces (256-byte payload per 512-byte block); see
+bootloader/inc/uf2format.h for the struct this has to match on the device
+side. No external dependencies, Python 3 only.
+
+Usage:
+ python uf2conv.py [--base 0x2000] [--family 0x68ed2b88]
+"""
+import argparse
+import struct
+
+UF2_MAGIC_START0 = 0x0A324655 # "UF2\n"
+UF2_MAGIC_START1 = 0x9E5D5157 # randomly selected, must match the device
+UF2_MAGIC_END = 0x0AB16F30 # ditto
+UF2_FLAG_FAMILYID_PRESENT = 0x00002000
+
+SAMD21_FAMILY_ID = 0x68ED2B88 # bootloader/inc/uf2format.h, #ifdef SAMD21
+PAYLOAD_SIZE = 256 # bytes per block; matches the upstream uf2conv.py convention
+
+
+def convert(bin_path: str, uf2_path: str, base_addr: int, family_id: int) -> int:
+ with open(bin_path, "rb") as f:
+ data = f.read()
+
+ # Pad to a whole number of blocks; the bootloader writes payloadSize
+ # bytes per block regardless of how much of it is real firmware.
+ if len(data) % PAYLOAD_SIZE != 0:
+ data += b"\x00" * (PAYLOAD_SIZE - len(data) % PAYLOAD_SIZE)
+ num_blocks = len(data) // PAYLOAD_SIZE
+
+ blocks = []
+ for block_no in range(num_blocks):
+ offset = block_no * PAYLOAD_SIZE
+ chunk = data[offset : offset + PAYLOAD_SIZE]
+ header = struct.pack(
+ " None:
+ parser = argparse.ArgumentParser(description=__doc__)
+ parser.add_argument("input", help="Path to the raw firmware .bin")
+ parser.add_argument("output", help="Path to write the .uf2 to")
+ parser.add_argument(
+ "--base",
+ type=lambda s: int(s, 0),
+ default=0x2000,
+ help="Flash base address the .bin was linked for (default: 0x2000, matches "
+ "variants/versapad/linker_scripts/gcc/flash_with_bootloader.ld)",
+ )
+ parser.add_argument(
+ "--family",
+ type=lambda s: int(s, 0),
+ default=SAMD21_FAMILY_ID,
+ help="UF2 family ID (default: SAMD21, 0x68ed2b88)",
+ )
+ args = parser.parse_args()
+
+ num_blocks = convert(args.input, args.output, args.base, args.family)
+ print(f"Wrote {args.output}: {num_blocks} blocks, base 0x{args.base:08x}")
+
+
+if __name__ == "__main__":
+ main()
diff --git a/upload_uf2.py b/upload_uf2.py
new file mode 100644
index 0000000..0448df3
--- /dev/null
+++ b/upload_uf2.py
@@ -0,0 +1,72 @@
+"""PlatformIO upload hook for env:versapad_usb.
+
+The board's actual bootloader (bootloader/, UF2/mass-storage) does not speak
+SAM-BA, so upload_protocol=sam-ba (the board.json default, inherited from an
+Arduino-Zero-style template) does not work here. This converts the built
+.bin to .uf2 and copies it onto the VERSABOOT mass-storage volume instead --
+Windows only for now, matching the rest of this project's dev environment.
+"""
+import ctypes
+import os
+import string
+import sys
+
+Import("env")
+
+sys.path.insert(0, env.subst("$PROJECT_DIR"))
+import uf2conv
+
+VOLUME_LABEL = "VERSABOOT"
+DRIVE_UNKNOWN = 0
+DRIVE_NO_ROOT_DIR = 1
+
+
+def find_versaboot_drive(label=VOLUME_LABEL):
+ for letter in string.ascii_uppercase:
+ root = f"{letter}:\\"
+ drive_type = ctypes.windll.kernel32.GetDriveTypeW(root)
+ if drive_type in (DRIVE_UNKNOWN, DRIVE_NO_ROOT_DIR):
+ continue
+ vol_name_buf = ctypes.create_unicode_buffer(261)
+ fs_name_buf = ctypes.create_unicode_buffer(261)
+ ok = ctypes.windll.kernel32.GetVolumeInformationW(
+ ctypes.c_wchar_p(root),
+ vol_name_buf,
+ ctypes.sizeof(vol_name_buf),
+ None,
+ None,
+ None,
+ fs_name_buf,
+ ctypes.sizeof(fs_name_buf),
+ )
+ if ok and vol_name_buf.value == label:
+ return root
+ return None
+
+
+def upload_via_uf2(source, target, env):
+ build_dir = env.subst("$BUILD_DIR")
+ bin_path = os.path.join(build_dir, "firmware.bin")
+ uf2_path = os.path.join(build_dir, "firmware.uf2")
+
+ if not os.path.isfile(bin_path):
+ print(f"error: {bin_path} not found (expected as a normal build product)")
+ env.Exit(1)
+
+ num_blocks = uf2conv.convert(bin_path, uf2_path, base_addr=0x2000, family_id=uf2conv.SAMD21_FAMILY_ID)
+ print(f"Wrote {uf2_path}: {num_blocks} blocks")
+
+ drive = find_versaboot_drive()
+ if drive is None:
+ print(f"error: no drive labeled '{VOLUME_LABEL}' found.")
+ print("Hold the bottom-right Cherry MX key while plugging in USB to enter the bootloader.")
+ env.Exit(1)
+
+ dest = os.path.join(drive, "firmware.uf2")
+ print(f"Copying {uf2_path} -> {dest}")
+ with open(uf2_path, "rb") as src, open(dest, "wb") as dst:
+ dst.write(src.read())
+ print("Upload triggers a reset into the app on the device side; no further action needed.")
+
+
+env.Replace(UPLOADCMD=upload_via_uf2)
diff --git a/variants/versapad/linker_scripts/gcc/flash_with_bootloader.ld b/variants/versapad/linker_scripts/gcc/flash_with_bootloader.ld
index f79fcbc..babb84e 100644
--- a/variants/versapad/linker_scripts/gcc/flash_with_bootloader.ld
+++ b/variants/versapad/linker_scripts/gcc/flash_with_bootloader.ld
@@ -6,7 +6,8 @@ SEARCH_DIR(.)
MEMORY
{
- rom (rx) : ORIGIN = 0x00002000, LENGTH = 0x0001E000 /* 120K (128K - 8K bootloader) */
+ rom (rx) : ORIGIN = 0x00002000, LENGTH = 0x0001DB00 /* 118.75K – Firmware (128K - 8K bootloader - 1.25K NVM) */
+ nvm (rx) : ORIGIN = 0x0001FB00, LENGTH = 0x00000500 /* 1.25K – Makros + Config, same layout as flash_without_bootloader.ld */
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* 16K */
}