forked from jappel/VersaMCU
de52b57041
Vendored and trimmed from microsoft/uf2-samdx1, adapted to the actual ATSAMD21G17D (128 KiB flash / 16 KiB RAM), fixing the flash/RAM-size mismatch that the previously commented-out SAM-BA bootloader target had (it assumed a 256 KiB SAMD21G18A). Builds as a standalone PlatformIO environment (bootloader/platformio.ini), no python2/make dependency. Compiles clean, fits in the 8 KiB bootloader region (7292/8192 bytes). Not yet flashed/verified on real hardware.
115 lines
3.2 KiB
C
115 lines
3.2 KiB
C
#include "uf2.h"
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// this actually generates less code than a function
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#define wait_ready() \
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while (NVMCTRL->INTFLAG.bit.READY == 0) \
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;
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void flash_erase_row(uint32_t *dst) {
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wait_ready();
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NVMCTRL->STATUS.reg = NVMCTRL_STATUS_MASK;
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// Execute "ER" Erase Row
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NVMCTRL->ADDR.reg = (uint32_t)dst / 2;
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
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wait_ready();
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}
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void flash_erase_to_end(uint32_t *start_address) {
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// Note: the flash memory is erased in ROWS, that is in
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// block of 4 pages.
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// Even if the starting address is the last byte
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// of a ROW the entire
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// ROW is erased anyway.
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uint32_t dst_addr = (uint32_t) start_address; // starting address
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while (dst_addr < FLASH_SIZE) {
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flash_erase_row((void *)dst_addr);
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dst_addr += FLASH_ROW_SIZE;
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}
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}
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void copy_words(uint32_t *dst, uint32_t *src, uint32_t n_words) {
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while (n_words--)
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*dst++ = *src++;
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}
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void flash_write_words(uint32_t *dst, uint32_t *src, uint32_t n_words) {
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// Set automatic page write
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NVMCTRL->CTRLB.bit.MANW = 0;
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while (n_words > 0) {
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uint32_t len = (FLASH_PAGE_SIZE >> 2) < n_words ? (FLASH_PAGE_SIZE >> 2) : n_words;
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n_words -= len;
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// Execute "PBC" Page Buffer Clear
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC;
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wait_ready();
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// make sure there are no other memory writes here
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// otherwise we get lock-ups
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while (len--)
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*dst++ = *src++;
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// Execute "WP" Write Page
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP;
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wait_ready();
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}
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}
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void flash_write(void) {
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uint32_t *src = (void *)0x20006000;
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uint32_t *dst = (void *)*src++;
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uint32_t n_rows = *src++;
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NVMCTRL->CTRLB.bit.MANW = 1;
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while (n_rows--) {
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wait_ready();
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NVMCTRL->STATUS.reg = NVMCTRL_STATUS_MASK;
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// Execute "ER" Erase Row
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NVMCTRL->ADDR.reg = (uint32_t)dst / 2;
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER;
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wait_ready();
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// there are 4 pages to a row
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for (int i = 0; i < 4; ++i) {
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// Execute "PBC" Page Buffer Clear
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC;
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wait_ready();
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uint32_t len = FLASH_PAGE_SIZE >> 2;
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while (len--)
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*dst++ = *src++;
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// Execute "WP" Write Page
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP;
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wait_ready();
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}
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}
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}
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// Skip writing blocks that are identical to the existing block.
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// only disable for debugging/timing
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#define QUICK_FLASH 1
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void flash_write_row(uint32_t *dst, uint32_t *src) {
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#if QUICK_FLASH
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bool src_different = false;
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for (int i = 0; i < FLASH_ROW_SIZE / 4; ++i) {
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if (src[i] != dst[i]) {
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src_different = true;
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break;
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}
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}
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if (!src_different) {
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return;
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}
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#endif
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flash_erase_row(dst);
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flash_write_words(dst, src, FLASH_ROW_SIZE / 4);
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}
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